Vendor: Frontgrade Gaisler Category: I2C / I3C

I²C Slave

The I²C slave core is a simple I²C slave that provides a link between the I²C bus and the AMBA APB.

Overview

The I²C slave core is a simple I²C slave that provides a link between the I²C bus and the AMBA APB. The core is compatible with the Philips I²C standard and supports 7- and 10-bit addressing with an optionally software programmable address. Standard-mode (100 kb/s) and Fast-mode (400 kb/s) operation are supported directly.

Key features

  • AMBA APB interface
  • Optional programmable I²C address - The initial address is configurable via a VHDL generic. The designer can choose to leave the core's address programmable via an APB mapped register.
  • 10-bit address support. If the core is configured without a hard coded address software may also configure the core to use 7-bit addressing.
  • Four main modes, core can be configured to force a master into wait mode by lowering the SCL line during reception and/or transmission. See GRIP manual for details.
  • Clock stretching

Block Diagram

I²C Slave block diagram

Specifications

Identity

Part Number
I²C Slave
Vendor
Frontgrade Gaisler
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Frontgrade Gaisler
HQ: Sweden

Learn more about I2C / I3C IP core

Frequently asked questions about I2C / I3C IP cores

What is I²C Slave?

I²C Slave is a I2C / I3C IP core from Frontgrade Gaisler listed on Semi IP Hub.

How should engineers evaluate this I2C / I3C?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this I2C / I3C IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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