Vendor:
Frontgrade Gaisler
Category:
USB
USB Debug Link
The Universal Serial Bus Debug Communication Link (USBDCL) provides an interface between an USB 2.0 bus and an AMBA-AHB bus.
Overview
The Universal Serial Bus Debug Communication Link (USBDCL) provides an interface between an USB 2.0 bus and an AMBA-AHB bus.
An external PHY compliant with either UTMI, UTMI+ or ULPI is needed to connect to the USB.
Architecture
The USBDCL is an AHB master and provides read and write access to the whole AHB address space using a simple protocol over two USB bulk endpoints. The USBDCL is a function implementation that utilizes the GRUSBDC device controller for the USB interface.
Protocol
The USBDCL protocol uses one IN and one OUT bulk endpoint (in addition to the mandatory control endpoint). Read and write commands to the AHB bus and write data are sent to the OUT endpoint. Read data is returned on the IN endpoint. The protocol is supported in the GRMON debug tool using libusb and provides maximum speeds of up to 30 MBit/s to the AHB bus over an USB 2.0 bus. The protocol specification is freely available so it is possible to develop own applications that utilize the USBDCL.
Block Diagram
USBDCL block diagram
What’s Included?
- VHDL RTL Source code
- Synplify project file
- Synthesis scripts
- Stand-alone VHDL test bench
- User's manual
- Template design for LEON3 processor
- FPGA evaluation board (optional)
- Drivers for Linux 2.6
Specifications
Identity
Part Number
USBDCL
Vendor
Frontgrade Gaisler
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Sweden
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Frequently asked questions about USB IP cores
What is USB Debug Link?
USB Debug Link is a USB IP core from Frontgrade Gaisler listed on Semi IP Hub.
How should engineers evaluate this USB?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this USB IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.