Super-speed USB3.0 Device Controller

USB3.0 SuperSpeed Device

The Super Speed USB bus is implemented as a separate dual-simplex data path consisting of two uni-directional differential links, one for transferring data from the host downstream to peripherals and one for transferring data from peripherals upstream to the host. The D+/D- signal pins defined by USB 2.0 are not used for Super Speed operation but are provided to allow for backward compatible operation.

Super-Speed USB Device Controller (VUSB30DC)

The Vinchip VUSB30DC core provides a USB functional device controller that conforms to the USB 3.0 specification for Super-Speed (5Gbps, 480 and 12 Mbps) functions. The core is user-configurable for up to 15 IN Endpoints and up to 15 OUT Endpoints in addition to Endpoint 0 (EP0). These additional Endpoints can be individually programmed for bulk/interrupt or isochronous transfers.

Each Endpoint requires an associated FIFO. The VUSB30DC has a RAM interface for connecting to a single block of synchronous dual-port RAM. The FIFO for Endpoint 0 is fixed at 64 bytes. The other Endpoint FIFOs may range upto the Maximum packet size of bytes in size and can buffer 1 or more packets. Separate FIFOs may be associated with each Endpoint.

The VUSB30DC provides a USB 3.0 Transceiver Interface (UTMI extension to usb3.0) to connect to an Super-Speed transceiver. Access to the FIFOs and internal control/status registers may be via a 32-bit AMBA AHB-compatible synchronous CPU interface via the AMBA AHB bridge.

The VUSB30DC has a RAM interface for connecting to the single block of synchronous RAM that is used for all the Endpoint FIFOs. The device also offers support for DMA access to the Endpoint FIFOs. (The VUSB30DC-AHB bridge includes DMA controller hooks.)

This Super-Speed function controller provides the entire USB packet of encoding, decoding, and checking interrupting the CPU only when the Endpoint data has been successfully transferred.

An Utility is provided for configuring the core to the user’s requirements.

• Complies with USB 3.0 standard for Super Speed(5.0 Gbps), Hi-Speed (480 Mbps) and Full-Speed (12 Mbps)
• Backward compatible with usb2.0 and the type A connectors.
• Technology and Process independent
• Data Interface is Dual-simplex, 4-wire differential signaling, separate from USB2.0 signaling.
• Supports Super speed UTMI transceiver interface with extension to the existing UTMI Interface for USB2.0
• Configurable up to 15 additional IN or OUT Endpoints
• Compatible USB transfer support for Control, Bulk, Interrupt and Isochronous transfers using USB3.0 Transaction/Handshake Packets and the Data Packets.
• Bus Transaction protocol is host directed and has asynchronous traffic flow. The packet traffic is explicitly routed.
• Parametrizable endpoint features for number, transfer type, direction of transfer, maximum packet size
• Built-in 32-bit synchronous AMBA AHB compatible CPU interface
• Support for DMA access to FIFOs
• Synchronous Dual Port RAM interface for FIFOs
• Supports suspend and resume signaling
• Fully synthesizable
• Support all standard, Vendor specific control transfer requests
• Utility for core configuration of device descriptors and to wire endpoints.

• Verilog source code and test-bench
• scripts for simulation and synthesis