Vendor: Great River Technology, Inc. Category: Video Transport

ARINC 818 Transceiver

Great River's ARINC 818 IP Core provides an easy way to implement ARINC 818–compliant interfaces in Xilinx and Altera PLDs.

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Overview

Great River's ARINC 818 IP Core provides an easy way to implement ARINC 818–compliant interfaces in Xilinx and Altera PLDs. The core can achieve ARINC 818 interfaces up to 4.25 Gbps. The core can be used for transmit-only, receive-only, or transmit-and-receive applications.

The core has many flexible compile-time settings, allowing for various link speeds, line segmentations, and line-synchronization methods. It can be configured for various resolutions and pixel packing methods. Ancillary data can use default values set at compile time, or data can be updated in real time via register interface.

Key features

  • Available for most Xilinx and Altera FPGAs with Gigabit transceivers
  • Supports all ARINC 818 Link speeds up to 8.5 Gbps
  • Simple pixel bus interface
  • Compile time configurable for ADVB video format (resolution, pixel type, etc.)
  • Supports transmit only, receive only, or full transceiver instantiation
  • Configurable for various line segmentations
  • Supports line synchronous transmission
  • Built-in pixel packing/unpacking
  • Link status & detection outputs (CRC_error, SOF/EOF_det, etc.)
  • Tx Object 0 Ancillary data real-time update
  • Tx Object 0 default values compile-time settable
  • Complete Object 0 Ancillary data recovery on Rx
  • Airborne Certification package available

Block Diagram

ARINC 818 (FC-AV) block diagram

What’s Included?

  • VHDL and Encripted VHDL files
  • Instantiation templates
  • VHDL test bench
  • UCF file templates
  • Coregen output files
  • User’s Guide
  • Optional Aerospace Certification Package
  • Optional Chipset and Reference Design

Specifications

Identity

Part Number
ARINC 818 (FC-AV)
Vendor
Great River Technology, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Great River Technology, Inc.

Learn more about Video Transport IP core

Enabling High Performance SoCs Through Multi-Die Re-use

This paper gives a high-level overview of a technique for rapid design of new IC designs using multiple dice packaged in a variety of aggregations allowing for differnent performance levels and price points to be achieved. The technique relies on a new high-bandwidth low pin-count communication channel between two or more dice.

An HDTV SoC Based on a Mixed Circuit-Switched / NoC Interconnect Architecture (STBus/VSTNoC)

This paper presents the interconnect solution adopted for an HDTV SoC developed in HVD division of STM. The SoC is a one-chip satellite HDTV set-top box IC developed in 65nm technology. The interconnect of this HDTV SoC is the first in STM implementing a mixed archi­tecture based on the circuit-switched interconnect named STBus and the new NoC interconnect named VSTNoC.

Frequently asked questions about Video Transport IP cores

What is ARINC 818 Transceiver?

ARINC 818 Transceiver is a Video Transport IP core from Great River Technology, Inc. listed on Semi IP Hub.

How should engineers evaluate this Video Transport?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Transport IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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