cjTAG IEEE 1149.7 Compact TAP Controller

The Compact TAP IP from Silvaco provides an IEEE 1149.7-compliant Test Access Port (TAP), enabling you to take advantage of IEEE 1149.7 features such as:

• 2-pin access to your on-chip IEEE 1149.1 test infrastructure
• Reduced scan times through shorter scan paths
• Efficient use of the 2-pin interface for both test and debug

The Compact TAP IP supports all mandatory and optional features of IEEE Std. 1149.7-2009.

IEEE Std 1149.7-2009

IEEE Std. 1149.7-2009 defines a next-generation Test Access Port (TAP), known as TAP.7, which extends IEEE 1149.1 TAP (TAP.1) functionality in several ways. Whereas IEEE 1149.1 was original developed as a solution for testing board-level interconnect, IEEE 1149.7 offers additional features to support increased chip integration, power management, application debug, and device programming. IEEE 1149.7 features are grouped into six classes, each of which is a superset of all the lower classes:

•   Class T0 maintains strict compliance to IEEE 1149.1 while also providing support for multiple IEEE 1149.1 TAPs on a single chip
•  Class T1 adds support for the IEEE 1149.7 command protocol, generation of functional and test resets, and power control
•  Class T2 adds the capability to bypass a chip’s system test logic, resulting in a 1-bit path for Instruction Register (IR) and Data Register (DR) scans
•  Class T3 adds support for connecting TAP.7 controllers in a 4-wire star topology (TAP.7 controllers connected in parallel)
•  Class T4 adds support for 2-pin operation (all signalling done using only TMS(C) and TCK(C)), which means that TDO and TDI can be removed or used for other functions
•   Class T5 adds support for up to two data channels for non-scan data transfers, with each data channel supporting up to sixteen on-chip data transfer clients

Configuration Options

Through hardware parameters, you can select the following optional features of the Compact TAP IP:

• Power-down support. If you choose to include power down support, the Compact TAP IP supports all IEEE 1149.7 powerdown modes and the power-down mode restore feature. Powerdown support requires a 32-kHz clock for the power-down timer
• Data channel (class T5) support:
• Transport function with 1 or 2 physical data channels (PDCs), each supporting up to 16 data channel clients
• Transport function with 0 PDCs (no data channel support; however, the Compact TAB IP remains online if the DTS initiates the transport protocol to a different target sharing the same DTS connection)
• No transport function or data channel

Interfaces

• Compact IEEE 1149.7 (JTAG) interface to off-chip DTS
• IEEE 1149.7 (JTAG) interface to on-chip test logic
• Power control/status interface to on-chip logic
• Functional/test reset interface to on-chip logic
• Configuration interface for node ID, JTAG device ID, decoupleat- startup, Controller ID, and TDI/TDO pin functions
• Data channel interface for optional data channels
• 32-kHz clock (optional, used for power-down mode support)
• Power-on reset
• DFT signals to control clock and reset for scan testing of the Compact TAP logic

• Supports IEEE 1149.7 classes T0–T5
• Supports all mandatory and optional scan formats: JScan0–3, MScan, OScan0–7, and SScan0–3
• Supports all IEEE 1149.7 mandatory and optional features, commands, and registers
• Firewall provides robust hot-connect protection by disabling TCK to on-chip test logic until the Debug Test System (DTS) deactivates hot-connect protection
• Partitioned along IEEE 1149.7-specified functional boundaries:
• Reset and Selection Unit (RSU) for class T0 optional features(contained within the APU)
• Extended Processing Unit (EPU) for extended (class T1–T3) operation
• Advanced Processing Unit (APU) for advanced (class T4 and T5) operation
• Separate blocks for clock and reset signal conditioning
• Data channel (class T5) logic is optional and is, therefore,isolated into a separate top-level module

• Synthesizable Verilog source code
• Integration testbench and tests
• Documentation
• Scripts for simulation and synthesis with support for common EDA tools