Display Stream Compression (DSC) standard was announced by Video Electronics Standards Association (VESA) in 2014 for video data …
- VESA DSC
Multimedia Interface IP cores provide the high-speed connectivity technologies required to transport video, audio, image, and display data across modern SoCs, ASICs, and electronic systems. These interfaces are essential for enabling seamless communication between processors, cameras, displays, sensors, and multimedia subsystems.
This category includes HDMI, DisplayPort, MIPI, V-By-One, and VESA DSC (Display Stream Compression) IP solutions. Available implementations may include controllers, PHYs, protocol stacks, bridge solutions, and complete subsystem IP supporting high-resolution displays, camera interfaces, video transport, display compression, and multimedia data exchange.
Compare multimedia interface IP cores by protocol standard, feature set, implementation model, and vendor offering to support your video, display, and media connectivity roadmap.
Display Stream Compression (DSC) standard was announced by Video Electronics Standards Association (VESA) in 2014 for video data …
Display Stream Compression (DSC) standard was announced by Video Electronics Standards Association (VESA) in 2014 for video data …
MIPI CSI-2 Transmitter for FPGA
MIPI CSI-2 Tx - IP core for FPGA which based on CSI-2 standard : Camera - Application Processer
MIPI CSI-2 Rx - IP core for FPGA which based on CSI-2 standard : Camera - Application Processor.
V-by-One/LVDS Tx IP, Silicon Proven in GF 22FDX
Based on internal equipment connections, the V-by-One® HS technology aims to transmit video signals at high data rates.
V-by-One/LVDS Rx IP, Silicon Proven in GF 22FDX
The V-by-One® HS technology aims to transmit video signals at a high data rate using internal equipment connections.
V-by-One Rx IP, Silicon Proven in SMIC 40LL
The V-by-One HS technology aims to transmit video signals at a high data rate using internal equipment connections.
V-by-One Tx IP, Silicon Proven in SMIC 40LL
V-by-One HS technology targets a high-speed data transmission of video signals based on the internal connection of equipment.
HDMI 1.4 Rx PHY & Controller IP, Silicon Proven in GF 65/55LPe
The HDMI receiver PHY (Physical layer), a single-port IP core, fully conforms with HDMI 1.4's requirements.
HDMI 1.4 Tx PHY & Controller IP, Silicon Proven in GF 65/55LPe
IP core that completely conforms with HDMI 1.4 requirements for physical layer HDMI transmitters For consumer electronics like DV…
Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processor…
Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processor…
Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processor…
IP
The VESA DSC and VDC-M IP cores deliver visually lossless video compression for mobile, AR/VR and automotive display applications.
The VESA DSC and VDC-M IP cores deliver visually lossless video compression for mobile, AR/VR and automotive display applications.
The HDMI Forward Error Correction (FEC) Transmitter IP Core implements Reed-Solomon FEC and symbol mapping/interleaving as specif…
The HDMI Forward Error Correction (FEC) Receiver IP Core implements Reed-Solomon FEC and symbol de-interleaving/de-mapping as spe…
MIPI CSI2 rev 2.0 transmitter/controller for FPGA, with 8 lanes and 2.5Gbps per lane
The SVTPlus-CSI2-F is a second generation MIPI CSI2-Tx transmitter IP core for FPGA implementations.
The BitCsi2Rx IP is a receiver for camera sensor signals, to be used in an FPGA or ASIC.