Vendor: VLSI Plus Ltd Category: MIPI

MIPI CSI2 rev 2.0 transmitter/controller for FPGA, with 8 lanes and 2.5Gbps per lane

The SVTPlus-CSI2-F is a second generation MIPI CSI2-Tx transmitter IP core for FPGA implementations.

Overview

The SVTPlus-CSI2-F is a second generation MIPI CSI2-Tx transmitter IP core for FPGA implementations. It complies with MIPI® CSI2 V2.0 and DPHY1.2 specifications, with up to 8 data lanes, at up to 2.5GBPS per lane. Total available bit rate is 20Gbps, supporting, for example, 7680x4320 (8K) images at 60fps

Key features

  • One clock lane, and from 1 to 8 data lanes
  • Simple interface – legacy parallel-video input, augmented by an Early-HD signal
  • Input interface – parallel 1, 2 or 4 pixels per clock
  • Can support any or all CSI2 2.0 pixel formats
  • Uses simple off-FPGA analog front-end – passive or active.
  • DPCM compression scheme according to CSI2 specification Annex A
  • Calibration Packet generation.
  • Easy-to-use Excel programming guide provided with the IP
  • Comprehensive customer support, until IP integration is successfully completed

Benefits

  • Up to 20GBps using DPHY 1.2
  • Simple user interface
  • interface to passive component or active off-FPGA analog front end
  • Supports pixel compression
  • Highly customized - can support any or all CSI2 video formats
  • 1,2 or 4 pixels per clock - allowing to trade lower internal clock rate for FPGA resources

What’s Included?

  • Verilog RTL
  • SDF
  • Documentation
  • Programmer Guide (Excel)

Specifications

Identity

Part Number
SVTPlus-CSI2-F
Vendor
VLSI Plus Ltd
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

VLSI Plus Ltd
HQ: Israel

Learn more about MIPI IP core

High Bit-Rate Controllers for MIPI CSI2

The imbalance between I/O speed and internal logic speed in integrated circuits has shifted in recent years in favor of the I/O. While in the past, the performance of integrated circuits was often limited by the I/O rate, today, in both ASICs and FPGAs, internal logic struggles to keep up with the I/O performance.

Generating High Speed CSI2 Video by an FPGA

In this article, we show how fast video streams conforming to MIPI CSI2 rev2.0 over MIPI DPHY rev1.2 can be generated, using VLSI Plus’ SVTPlus-CSI2-F IP core, with simple off-FPGA analog front-end. The high bit rates can be achieved with a relatively slow FPGA clock frequency, trading off FPGA resources for simple timing closure.

Frequently asked questions about MIPI IP cores

What is MIPI CSI2 rev 2.0 transmitter/controller for FPGA, with 8 lanes and 2.5Gbps per lane?

MIPI CSI2 rev 2.0 transmitter/controller for FPGA, with 8 lanes and 2.5Gbps per lane is a MIPI IP core from VLSI Plus Ltd listed on Semi IP Hub.

How should engineers evaluate this MIPI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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