Display Stream Compression (DSC) standard was announced by Video Electronics Standards Association (VESA) in 2014 for video data …
Overview
Display Stream Compression (DSC) standard was announced by Video Electronics Standards Association (VESA) in 2014 for video data compression and has been also adopted into the VESA's eDP v1.4 and the MIPI DSI standard.
Compliant with the VESA DSC 1.2a and 1.2b standards, CYBDSC2e
IP core supports various coding schemes (MMAP, BP, MPP, ICH) as well as color formats in YCbCr 4:4:4, 4:2:2, 4:2:0 and RGB. It transfers more pixel data over display links to save memory size in embedded frame buffers in display driver ICs and performs visually lossless compression, low gate count and latency for ultra-high definition display applications. It can be fastly and easily integrated into ASIC and FPGA applications for 4K / UHD TV, DisplayPort 1.4, USB Type-C device and AR / VR product.
CYB-DSC2e is available now for display designs with high performance but low risk and cost.
Key features
Compliant with the VESA DSC 1.2a and 1.2b standards
Perform encoding
Support MMAP, BP, MPP and ICH
Support YCbCr 4:4:4, 4:2:2, 4:2:0 and RGB
Support 8/10/12 bits per component
Support 3 pixels per clock
Configurable features for gate count, speed or power requirement
Frequently asked questions about VESA DSC IP cores
What is DSC Encoder?
DSC Encoder is a VESA DSC IP core from Cybertek Solution Inc. listed on Semi IP Hub.
How should engineers evaluate this VESA DSC?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this VESA DSC IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.