Overview
Display Stream Compression (DSC) standard was announced by Video Electronics Standards Association (VESA) in 2014 for video data compression and has been also adopted into the VESA's eDP v1.4 and the MIPI DSI standard.
Compliant with the VESA DSC 1.2a and 1.2b standards, CYBDSC2e
IP core supports various coding schemes (MMAP, BP, MPP, ICH) as well as color formats in YCbCr 4:4:4, 4:2:2, 4:2:0 and RGB. It transfers more pixel data over display links to save memory size in embedded frame buffers in display driver ICs and performs visually lossless compression, low gate count and latency for ultra-high definition display applications. It can be fastly and easily integrated into ASIC and FPGA applications for 4K / UHD TV, DisplayPort 1.4, USB Type-C device and AR / VR product.
CYB-DSC2e is available now for display designs with high performance but low risk and cost.
Learn more about VESA DSC IP core
The integration of VESA Display Stream Compression (DSC) and MIPI Display Serial Interface (DSI) in a System-on-Chip (SoC) offers significant benefits for high-resolution display systems. This whitepaper discusses the challenges involved in integrating these technologies and provides insights into overcoming them.
From the first monochrome mobile displays to today’s ultra-high-definition automotive dashboards and immersive AR/VR headsets, MIPI technology has quietly become the backbone of modern data connectivity. Let’s explore how MIPI standards have evolved, the markets they serve, and why Rambus is at the forefront of this transformation.
Over the past decade, we have seen generations of new products with increasingly sophisticated display feature sets. Each new generation pushes the boundaries of display technology even further with higher resolutions, faster refresh rates, and increased pixel depth at the forefront of these developments.
As automotive displays become part of the safety surface, traditional host-dependent display architectures are showing their limits. In this article, Trilinear outlines how a RISC-V supervised DisplayPort subsystem can provide isolated control, deterministic fault handling, and a more auditable architecture for advanced automotive display platforms.
