256x8 Bits OTP (One-Time Programmable) IP, TSMC 0.13um 1.5V/3.3V LP Process
The AT256X8T130LP0AA is organized as a 256-bit by 8 one-time programmable (OTP).
The ATO00256X1TS180MSG3NA is organized as a 256 bit by 1 one-time programmable (OTP).This is a kind of non-volatile memory fabric…
DDR4/ LPDDR4/ DDR3L PHY IP - 1866Mbps (Silicon Proven in TSMC 28HPC+)
The LPDDR4/ DDR4/ DDR3L Combo PHY IP offers low latency and supports throughput of up to 1866Mbps.
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 40LP
Data rates for the DisplayPort transmitter PHY version 1.4 range from 1.62Gbps (RBR) to 5.4Gbps (HBR2).
USB 3.1 Gen1/Gen2 PHY IP, Silicon Proven in TSMC 28HPC+
This PHY IP supports both USB 3.1 Gen1 & Gen2.
PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 28HPCP
With compatibility for PIPE 4.4 interface protocol, this Peripheral Component Interconnect Express (PCIe) x4 PHY complies with PC…
DDR4/ LPDDR4/ DDR3L PHY IP - 3200Mbps (Silicon Proven in TSMC 12FFC)
The DDR4/ DDR3L/ LPDDR4 Combo PHY IP provides low latency and enables up to 3200Mbps throughput.
In-Chip Monitoring Subsystem for Process, Voltage & Temperature (PVT) Monitoring, TSMC 28HPC+
A full suite of embedded monitoring IP managed by a PVT controller with standard interfaces, creates a subsystem dedicated to max…
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 28HPC+
The DisplayPort transmitter PHY version 1.4 supports data rates between 1.62Gbps (RBR) to 5.4Gbps (HBR2).
PCIe is the most common protocol in high speed serial standards to connect components in embedded systems.
USB 3.0/ PCIe 2.0 Combo PHY IP, Silicon Proven in TSMC 28HPC+
The Combo PHY is a USB 3.0 and PCIe 2.0 PHY IP solution designed for a mobile and data consumer applications in TSMC 28nm process.
USB 2.0 PHY IP, Silicon Proven in TSMC 40LP/LL
The USB2.0 PHY IP is an entire physical layer (PHY) IP solution built for high performance and low power consumption.
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 55ULP/65ULP
The PCIe2.0 PHY IP is a physical layer (PHY) IP solution designed for mobile and consumer applications.
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 22ULP/ULL
The PCIe2.0 PHY IP is an all-in-one physical layer (PHY) IP solution for mobile and consumer applications.
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 28HPCP
The PCIe2.0 PHY IP is a fully - featured physical layer (PHY) IP solution for mobile and consumer applications.
Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 40LP
This Display Port v1.4 Rx PHY IP Core supports Channel capacity, offering programmable analog characteristics like CDR Bandwidth,…
USB 3.0 PHY IP, Silicon Proven in TSMC 28HPC+
A Universal Serial Bus (USB) transceiver which is provided for peripheral devices.
PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
This Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 4.0 Base Specification with support of PIPE 4…
3.3V Wide-Range General Purpose Inline I/O Pad Set
The 3.3V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of I/O power, core po…
USB 2.0 PHY IP, Silicon Proven in TSMC 28HPC+
The USB2.0 PHY IP is an entire physical layer (PHY) IP solution built for high performance and low power consumption.