USB 2.0 PHY IP, Silicon Proven in TSMC 40LP/LL
The USB2.0 PHY IP is an entire physical layer (PHY) IP solution built for high performance and low power consumption.
- USB 2.0
- TSMC
- 40nm
- LP
- In Production
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
USB 2.0 PHY IP, Silicon Proven in TSMC 40LP/LL
The USB2.0 PHY IP is an entire physical layer (PHY) IP solution built for high performance and low power consumption.
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 55ULP/65ULP
The PCIe2.0 PHY IP is a physical layer (PHY) IP solution designed for mobile and consumer applications.
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 22ULP/ULL
The PCIe2.0 PHY IP is an all-in-one physical layer (PHY) IP solution for mobile and consumer applications.
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 28HPCP
The PCIe2.0 PHY IP is a fully - featured physical layer (PHY) IP solution for mobile and consumer applications.
Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 40LP
This Display Port v1.4 Rx PHY IP Core supports Channel capacity, offering programmable analog characteristics like CDR Bandwidth,…
USB 3.0 PHY IP, Silicon Proven in TSMC 28HPC+
A Universal Serial Bus (USB) transceiver which is provided for peripheral devices.
PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
This Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 4.0 Base Specification with support of PIPE 4…
USB 2.0 PHY IP, Silicon Proven in TSMC 28HPC+
The USB2.0 PHY IP is an entire physical layer (PHY) IP solution built for high performance and low power consumption.
Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 28HPC+
Display port 1.4 Rx IP supports Channel bandwidth Up to 5.4bps per channel (HBR2), Programmable analog characteristics like CDR B…
MIPI M-PHY v3.1 IP, Silicon Proven in TSMC 28HPC+
The MIPI M-PHY Gear 3 IP is compliant with the latest MIPI Feature Storage IP Solution SerDes PHY Product Brief Alliance M-PHY v3…
MIPI D-PHY Tx IP, Silicon Proven in UMC 55LP
Version 1.2 of the D-PHY specification is completely complied with by the MIPI D-PHY Analog TX IP Core.
PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 28HPCP
This Peripheral Component Interconnect Express Gen3 PHY is compliant with PCIe 3.0 Base Specification with support of PIPE 4.3 in…
HDMI 1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 65/55LP
HDMI transmitter PHY (Physical layer) IP core which is fully compliant with HDMI 1.4 specification.
HDMI 1.3 Tx PHY & Controller IP, Silicon Proven in TSMC 40LP
HDMI transmitter PHY (Physical layer) IP core which is fully compliant with HDMI 1.3 specification.
HDMI 1.3 Rx PHY & Controller IP, Silicon Proven in TSMC 40LP
HDMI receiver PHY (Physical layer) IP is single-port core which is fully compliant with HDMI 1.3a specification.
HDMI 1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 65/55LP
HDMI receiver PHY (Physical layer) is a single-port IP core which is fully compliant with HDMI 1.4 specification.
LVDS-based IOs The Bi-directional LVDS is in production from 90nm CMOS to 16/12nm FinFET and taped out in 7nm FinFET.
The TRC5024CPA is a four lane Gen 1 and 2 PCI Express Physical layer (Phy) Phy IP core, delivering high-speed serial data transmi…
Clock and Data Recovery of HDB3/B3ZS coded signals
An all-digital solution suitable for clock/data recovery of HDB3/B3ZS coded signals.
Quad 1.06/1.25/2.125/1.56/2.5/3.125 Gbps Backplane SerDes
TRC3104SBA is a Quad SerDes transceiver device, capable of transmitting 1.06 to 3.125Gb/s signals over Backplane, Fiber Channel, …