IP Accelerated (Bye Bye EDA 360)
Eric Esteve
Vendor:
T2M GmbH
Category:
MIPI PHY
MIPI D-PHY Tx IP, Silicon Proven in UMC 55LP
Version 1.2 of the D-PHY specification is completely complied with by the MIPI D-PHY Analog TX IP Core.
Overview
Version 1.2 of the D-PHY specification is completely complied with by the MIPI D-PHY Analog TX IP Core. It is compatible with the Display Serial Interface and the MIPI Camera Serial Interface (CSI-2) (DSI protocols). With one clock lane and four data lanes, it is a Tx PHY. A digital back end controls the I/O operations, and an analogue front end produces and receives electrical level signals. auto-calibrating internal termination resistor The D-PHY is a MIPI DSI PHY (MIPI TX DPHY) and has a PLL, a clock lane, four data lanes, and a clock lane. It can be used as a GPIO bank with a 5V tolerance.
Key features
- Compliant to MIPI Alliance Standard for
- D-PHY specification Version 1.2
- Supports standard PPI interface compliant to MIPI Specification
- Supports synchronous transfer at high-speed mode with a bit rate of 80-2500 Mb/s
- Supports asynchronous transfer at low power mode with a bit rate of 10 Mb/s
- Supports ultra-low power mode, high-speed mode and escape mode
- Supports one clock lane and up to four data lanes
- Data lanes support transfer of data in high-speed mode
- Supports error detection mechanism for sequence errors and contentions
- Supports contention detection
- Configurable skew option for each Clock and Data lanes
- Testability for TX, RX and PLL
- Silicon Proven in UMC 55LP.
Block Diagram
MIPI D-PHY Tx IP in 55LP block diagram
What’s Included?
- GDSII & layer map
- Place-Route views (.LEF)
- Liberty library (.lib)
- Verilog behaviour model
- Netlist & SDF timing
- Layout guidelines, application notes
- LVS/DRC verification reports
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 28nm | HPC+ | In Production |
Specifications
Identity
Part Number
MIPI D-PHY Tx IP in 55LP
Vendor
T2M GmbH
Type
Silicon IP
Standards & Interfaces
MIPI PHY
MIPI D-PHY
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Germany
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Frequently asked questions about MIPI PHY IP
What is MIPI D-PHY Tx IP, Silicon Proven in UMC 55LP?
MIPI D-PHY Tx IP, Silicon Proven in UMC 55LP is a MIPI PHY IP core from T2M GmbH listed on Semi IP Hub. It is listed with support for tsmc In Production.
How should engineers evaluate this MIPI PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.