Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
32-bit Floating-point Square-root IP Core
High-speed fully pipelined 32-bit floating-point square-root function based on the IEEE 754 standard.
IEEE 802.11n/ac/ax (WiFi) LDPC Decoder and Encoder
The WiFi family of standards (IEEE 802.11) is used for Wireless Local Area Networks (WLANs).
Generic Open Source Viterbi Decoder
Convolutional codes are widely adopted in wireless communication systems for forward error correction.
DVB-C2 Receiver (including LDPC and BCH decoder)
DVB-C2 (Digital Video Broadcast – Cable 2nd Generation) is an ETSI standard of the second generation for digital data transmissio…
IEEE 802.15.3c (60 GHz PHY) Multi-Gbit/s LDPC Decoder
The IEEE 802.15 working group specifies standards targeting the wireless personal area network (WPAN).
GEO-Mobile Radio (GMR) LDPC Decoder
GEO-Mobile Radio (GMR) is an ETSI standard for satellite phones.
1Gbit/s LDPC Decoder and Encoder (WiMedia UWB)
The solution from Creonic for data rates of up to 1 Gbit/s offers outstanding efficiency in terms of implementation complexity.
The BCH decoder has four main functional blocks along with memory blocks.
Highest code density, Low Power 32-bit Processor with optional DSP
The Beyond BA22 32-bit processor offers the highest code density of any processor in its class, reducing die size and memory requ…
4/8-bit mixed-precision NPU IP
Features a optimized network model compiler that reduces DRAM traffic from intermediate activation data by grouped layer partitio…
High-performance, deterministic hardware IP for real-time signal processing, control algorithms, and embedded AI acceleration.
256 bit per clock LZ4 Decompressor Core
Ultra low-Latency Single-Engine Decompressor Core
The SiFive® Performance™ P570 Gen 3 brings fully out-of-order support coupled with support for the most comprehensive set of RVA2…
Compact and low energy consumption to provide the performance you need in radar, lidar, and communications processing at ultra-low area and energy cost
DVBS2_DEMOD.vhd performs the demodulation based on three tracking loops: carrier tracking (for coherent demodulation), symbol tim…
RISC-V-Based, Open Source AI Accelerator for the Edge
Coral NPU is a machine learning (ML) accelerator core designed for energy-efficient AI at the edge.
License our analog in-memory compute macros (e.g., 32×32 X1 crossbars) for integration into your ASIC or SoC.
NavIC LDPC Decoder
Shaped Offset Quadrature Phase Shift Keying - Telemetry Group (SOQPSK-TG) is a type of QPSK/OQPSK modulation.
LZ4SNP-C is a custom hardware implementation of a lossless data compression engine that complies with the LZ4 and Snappy compress…