IEEE 802.3bj Reed-Solomon Encoder and Decoder
IEEE 802.3bj was developed in response to the rapid growth of server, network and internet traffic.
- Channel Coding
- Now
- IEEE 802.3bj
Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
IEEE 802.3bj Reed-Solomon Encoder and Decoder
IEEE 802.3bj was developed in response to the rapid growth of server, network and internet traffic.
Mobiveil’s 50G PON LDPC Encoder/Decoder offers industry- LDPC error correction in a low-power, small-footprint, high-reliability …
The DVB-S2X demodulator is a low-complexity high-performance solution that allows for symbol rates of up to 100 MSymb/s on FPGAs …
The transform computation is based on a new matrix formulation of the discreet Fourier transform1 (DFT) which decomposes it into …
This FFT circuit employs unique architectural characteristics, different than any other FFT implementation.
Variable FFT (run time choice of FFT size)
This FFT circuit employs unique architectural characteristics, different than any other FFT implementation.
LTE Single Carrier FFT Circuit
Centar's DFT circuit can perform all 35 transform sizes needed to implement the LTE SC-FDMA protocols.
The DVB-S2X decoder is a silicon-proven, scalable solution that allows for symbol rates of up to 100 MSymbols/s on FPGAs.
ASIP-2 Programmable Filter Engine
Application Specific Instruction Set Processors (ASIPs) possess an instruction set which is tailored to benefit a specific applic…
WCDMA Release 9 compliant Viterbi Decoder
The Lekha IP – 3GPP WCDMA Viterbi Decoder IP Core V1.0 addresses the implementation of the Viterbi Decoder defined as part of the…
DVB-S2 (Digital Video Broadcast – Satellite 2nd Generation) is an ETSI standard of the second generation for digital data transmi…
DVB-CID (Digital Video Broadcast - Carrier Identification System) is an ETSI standard for interference prevention within digital …
Constant False Alarm Rate Processor (CFAR)
The eSi-CFAR is an high throughput Constant False Alarm Rate (CFAR) IP core, whose main application area is automotive driver ass…
High bit rate Turbo Decoder core for 3GPP LTE/ LTE A
The Lekha IP – 3GPP LTE Turbo Decoder IP Core V1.0 addresses the decoder implementation for the turbo coded transport channel com…
LMS Adaptive Channel Equalizer
The AH1001_LEQ LMS Adaptive Channel Equalizer (LEQ) FPGA core provides a 17-tap Least Mean Squares (LMS) signed-error adaptive Ch…
DVB-RCS (Digital Video Broadcasting – Interaction channel for satellite distribution systems) is an established ETSI standard for…
IEEE 802.11ad (WiGig 60GHz) LDPC Decoder
The WiGig standard (IEEE 802.11ad) delivers data rates of up to 7 Gbit/s and hence outperforms the current IEEE 802.11n standard …
MIMO (Multiple Input Multiple Output) techniques are being used more and more in recent and upcoming standards since they drastic…
DVB-RCS2 (Digital Video Broadcast – Second Generation DVB Interactive Satellite System) is the latest ETSI standard of the second…
DVB-S2 BCH and LDPC Encoder and Decoder
DVB-S2 (Digital Video Broadcast - Satellite 2nd Generation) is an ETSI standard of the second generation for digital data transmi…