x2 - 8-bit RISC Microcontroller

The DFPIC1655X is a low-cost, high performance, 8-bit, fully static soft IP Core, intended to operate with fast memory. The core has been designed with a special concern about low power consumption, in combination with high performance.
The DFPIC1655X software is compatible with the industry standard PIC 16XXX Microcontrollers. It has a modified RISC architecture (2 times faster than original implementation).
The DFPIC1655X has enhanced core features, configurable hardware stack and multiple internal and external interrupt sources. The separate instruction and data buses allow a 14-bit wide instruction word, with a separate 8-bit wide data.

The power-down SLEEP mode allows user to significanlty reduce power consumption and "wake up" the controller, through several external and internal interrupts and resets. An integrated Watchdog Timer with it's own dedicated clock signal, provides protection against software lock-up.
The DFPIC1655X Microcontroller fits perfectly in applications ranging from high-speed automotive and appliance motor control, to low-power remote transmitters/receivers, pointing devices and telecom processors. Built-in power save mode and small used area in programmable devices, make this IP core perfect for applications, with space and power consumption limitations.
DFPIC1655X is delivered with fully automated testbench, complete set of tests and DoCD  on-chip hardware debugger , allowing easy package validation, at each stage of SoC design flow.

Each of the DCD's PIC Core, has built-in support for DCD Hardware Debug System, called DoCD . It is a real-time hardware debugger, which provides debugging capability of a whole System on Chip (SoC).

Unlike other on-chip debuggers, the DoCD provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, SFRs, including user defined peripherals, data and program memories.

• Software compatible with PIC16C55X industry standard
• Harvard RISC architecture
  • 2 times faster, compared to original implementation
• 35 instructions
• 14 bit wide instruction word
• Up to 32 kB of internal Data Memory
• Up to 64K bytes of Program Memory
• Configurable hardware stack
• Power saving SLEEP mode
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Technology independent HDL Source Code

• HDL Source Code
• Testbench environment
  • Automatic Simulation macros
  • Tests with reference responses
• Synthesis scripts
• Technical documentation
• 12 months of technical support