x2 - 8-bit RISC Microcontroller

The DFPIC165X is a low-cost, high performance, 8-bit, fully static soft IP Core, intended to operate with fast memory (typically on-chip). The core has been designed with a special concern about low power consumption.
The DFPIC165X software is compatible with the PIC16C54, PIC16C55, PIC16C56, PIC16C57 and PIC16C58 industry standards. It has a modified RISC architecture (2 times faster than original implementation).
The DFPIC165X has enhanced core features and configurable hardware stack. The separate instruction and data buses allow a 12 bit wide instruction word, with the separate 8-bit wide data. The DFPIC165X typically achieves a 2:1 code compression and a 8:1 speed improvement, over other 8-bit microcontrollers in its class. The Core has 24 I/O lines and an 8-bit timer/counter, with an 8-bit programmable prescaller.
The power-down SLEEP mode allows user, to reduce power consumption. User can "wake up" the controller from SLEEP, through an user reset or watchdog overflow. An integrated Watchdog Timer (with it's own clock signal) provides protection against software lock-up.
The DFPIC165X Microcontroller fits perfectly in applications ranging from high-speed automotive and appliance motor control, to low-power, remote transmitters/receivers, pointing devices and telecom processors. Built-in power save mode and small used area in programmable devices, make this IP core perfect for applications with space and power consumption limitations.
The DFPIC165X is delivered with fully automated testbench and complete set of tests, allowing easy package validation, at each stage of SoC design flow.

• Software compatible with industry standard PIC16C5X
• Harvard RISC architecture
• 2 times faster, compared to original implementation
• 33 instructions
• 12 bit wide instruction word
• Up to 256 bytes of internal Data Memory
• Up to 4K bytes of Program Memory
• Configurable hardware stack
• Power saving SLEEP mode
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Technology independent HDL Source Code

• HDL Source Code
• Testbench environment
  • Automatic Simulation macros
  • Tests with reference responses
• Synthesis scripts
• Technical documentation
• 12 months of technical support