S2C Named Andes Technology’s 2026 Partner of the Year
本月，头部数字EDA企业思尔芯宣布，荣获RISC-V处理器IP领导厂商Andes晶心科技（Andes Technology）颁发的“2026年度最佳合作伙伴”奖项。该荣誉旨在表彰思尔芯在RISC-V生态共建、原型验证平台支撑及联合市场拓展中与Andes晶心深度协同、持续创造客户价值的突出表现。
Vendor:
Andes Technology Corp.
Category:
CPU
Highly-Configurable 32-bit Processor
The AndesCore N9 Family is intended for deeply embedded applications that require optimal interrupt response features, including …
Overview
The AndesCore N9 Family is intended for deeply embedded applications that require optimal interrupt response features, including wireless networking and sensors, micro-controllers, automotive electronics, and industrial control systems. The low-power N9 Family of processors features low gate count, low interrupt latency, and low-cost debug. The processor family provides superior performance and excellent interrupt handling response while meeting the challenges of low dynamic and static power constraints.
The AndesCore N9 Family of CPU cores implement v3, the AndeStar™ patented 32-bit RISC-style CPU architecture. The designer can configure certain parameters to adjust the CPU’s size, power, and performance. For example, the N9 core can be configured with 16 or 32 general registers, two or three read ports on the register file, one or two write ports, a fast or a small multiplier, a 24-bit or 32-bit address space, and different bus (APB, AHB, AHB-Lite, AXI) interfaces to connect to the rest of the system.
The AndesCore N9 Family of CPU cores implement v3, the AndeStar™ patented 32-bit RISC-style CPU architecture. The designer can configure certain parameters to adjust the CPU’s size, power, and performance. For example, the N9 core can be configured with 16 or 32 general registers, two or three read ports on the register file, one or two write ports, a fast or a small multiplier, a 24-bit or 32-bit address space, and different bus (APB, AHB, AHB-Lite, AXI) interfaces to connect to the rest of the system.
Key features
- High performance V3 ISA on a compact CPU architecture
- Superior total performance deliverable
- Efficient pipeline optimized for Local Memory accesses
- High configurability including AXI bus support
Block Diagram
AndesCore ™ N968A block diagram
Benefits
- Performance
- Highly compact program size through AndeStar™ V3 ISA
- Static branch predication to speed up loop control
- Low latency vectored interrupt
- Optional saturation instructions for efficient voice applications
- Processor state bus to simplify SoC design and debugging
- Flexibility
- All-C Embedded Programming
- Stack protection hardware to help determining stack size needed,
- and detect runtime overflow error
- Support boot-up from Instruction Local Memory
- Power management
- Low power modes initiated by SW or SoC
- PowerBrake technology to reduce peak power consumption
Applications
- Wireless device
- Wireless charger
- Touch screen controller
- Storage device
- Industrial control
- Biometrics device
- GPS
- Game console
Specifications
Identity
Part Number
AndesCore ™ N968A
Vendor
Andes Technology Corp.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
R.O.C
Learn more about CPU IP core
Andes Technology Honors Quintauris as 2026 Partner of the Year
This award recognizes Quintauris’ exceptional dedication to develop reference architectures and advancing mass-market commercialization for the RISC-V ecosystem with Andes.
Andes Technology Empowers RISC-V Developers with Its New Streamlined IDE, RVBuilder
Based on Visual Studio Code (VS Code), it is integrated, lightweight, and designed to streamline the development experience by bringing Andes’ industry-leading toolchain and advanced debugging capabilities directly into the most popular integrated development environment (IDE).
Andes Technology’s D23-SE RISC-V Processor Achieves ISO 26262 ASIL‑B and ASIL‑D Certification for Functional Safety Applications
Built upon the production-proven D23 architecture, the 32-bit D23-SE processor is specifically engineered for safety-critical systems requiring deterministic performance, robust security mechanisms, and accelerated SoC compliance workflow.
Andes Technology Unveils Next-Generation AI Solutions: AndesAIRE™ AnDLA™ I370 v2.0 and NN SDK v1.2.0 for Advanced ViT, VLM, and SLM at the Edge
This milestone release addresses one of the industry’s most challenging hurdles: enabling resource-heavy Transformer architectures such as Vision Transformers (ViT), Vision-Language Models (VLMs), and Small Language Models (SLMs) to execute efficiently on power- and cost-constrained edge platforms.
Andes Technology and Mirabilis Design Announce Collaboration on System-Level Models for Andes RISC-V Processor IP
Validated Architecture Models Enable Early Design Exploration and Pre-RTL Optimization
Frequently asked questions about CPU IP cores
What is Highly-Configurable 32-bit Processor?
Highly-Configurable 32-bit Processor is a CPU IP core from Andes Technology Corp. listed on Semi IP Hub.
How should engineers evaluate this CPU?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.