Vendor: Applied Brain Research Category: NPU

Low power AI accelerator

For device makers, a small, inexpensive, low-power chip that can run the large AI models is needed to lead the market with their …

Overview

For device makers, a small, inexpensive, low-power chip that can run the large AI models is needed to lead the market with their device features. A very efficient and low-cost, low-power way to achieve this is to compress large AI models and design a computer chip that runs such an AI compression algorithm. ABR has done exactly this with our patented AI time-series compression algorithm, called the Legendre Memory Unit (LMU).
The LMU was engineered by emulating the algorithm used by time-cells, a kind of neuron, in the human brain. The work was done by ABR in partnership with the neuroscience engineering research lab at U Waterloo where our company was spun out of.

Key features

  • Complete speech processing at less than 100W
  • Able to run time series nerworks for signal and speech
  • 10X more efficient than traditional NNs

Benefits

  • Ultra low power
  • Run complete speech stack on the chip
  • Add voice interface to any device at less than 100mW
  • Comprehensive signal processing for health IoT devices

Applications

  • IoT devices
  • Wearables
  • Medical devices
  • Consumer Devices

What’s Included?

  • RTL
  • Synthesis Scripts
  • Test environment

Specifications

Identity

Part Number
TSP IP
Vendor
Applied Brain Research
Type
Silicon IP

Provider

Learn more about NPU IP core

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Frequently asked questions about NPU IP cores

What is Low power AI accelerator?

Low power AI accelerator is a NPU IP core from Applied Brain Research listed on Semi IP Hub.

How should engineers evaluate this NPU?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this NPU IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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