Vendor: Global IP Core Sales Category: Channel Coding

DVB-S2X Wideband LDPC/ BCH Decoder

The DVB-S2X Wideband LDPC Decoder is a FEC core decoder for Digital Video Broadcasting via Satellite.

Overview

The DVB-S2X Wideband LDPC Decoder is a powerful FEC core decoder for Digital Video Broadcasting via Satellite. It implements extensions to the DVB-S2 design for better performance and efficiency as well as robust service availability.

Key features

  • Irregular parity check matrix
  • Layered Decoding
  • Minimum sum algorithm
  • Soft decision decoding
  • BCH decoder works on GF (2m) where m=16 or 14 and corrects up to t errors, where t = 8, 10 or 12
  • ETSI EN 302 307-1 V1.4.1 (2014-11) compliant
  • Medium codeword length
  • Extra code rates for finer gradation
  • Adding 64, 128, 256 APSK
  • Very low SNR down to -10dB
  • Wideband support

Benefits

  • Improved performance
  • Improved efficiency w.r.t. Shannon’s limit
  • Finer gradation of code rate and SNR
  • Very high data rate
  • Maximum service availability at highest efficiency
  • Enables cross layer optimization

What’s Included?

  • Synthesizable Verilog
  • System Model (Matlab)
  • Verilog Test Benches
  • Documentation

Specifications

Identity

Part Number
DVB-S2X Wideband LDPC/ BCH Decoder
Vendor
Global IP Core Sales
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Global IP Core Sales
HQ: Germany

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Frequently asked questions about Channel Coding IP cores

What is DVB-S2X Wideband LDPC/ BCH Decoder?

DVB-S2X Wideband LDPC/ BCH Decoder is a Channel Coding IP core from Global IP Core Sales listed on Semi IP Hub.

How should engineers evaluate this Channel Coding?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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