U74 High performance Linux-capable RISC V processor
The SiFive U74 Standard Core is a single-core instantiation of the world's highest performance RISC-V application processor, capa…
- RISC-V
CPU IP cores provide general-purpose processing for application, control, and system software workloads in modern SoC and ASIC designs.
These IP cores deliver programmable compute for embedded and high-performance SoCs, often serving as the central control or application processor in the architecture
This catalog allows you to compare CPU IP cores from leading vendors based on performance, power efficiency, software ecosystem, and process node compatibility.
Whether you are designing application processors, embedded systems, networking equipment, or compute SoCs, you can find the right CPU IP for your application.
U74 High performance Linux-capable RISC V processor
The SiFive U74 Standard Core is a single-core instantiation of the world's highest performance RISC-V application processor, capa…
S76 MC Quad-core 64-bit embedded processor
The SiFive S76-MC Standard Core is a high-performance 64-bit quad-core embedded processor which is fully-compliant with the RISC-…
S54 64-bit embedded RISC V processor
The SiFive S54 Standard Core is a 64-bit embedded processor that is fully-compliant with the RISC-V ISA.
S51 Low-power 64-bit MCU RISC V core
The SiFive S51 Standard Core is a 64-bit embedded processor, fully compliant with the RISC-V ISA.
S21 Area optimized 64-bit RISC V processor
The SiFive S21 Standard Core is a full-featured 64-bit embedded processor based on the S2 Series.
64-bit CPU with RISC-V Vector Extension
The 64-bit NX27V is a vector processor with 5-stage scalar pipeline that supports the latest RISC-V specification, including the …
Compact High-Speed 32-bit CPU Core with MemBoost and PMA
The 32-bit A27 is a 5-stage processor that supports the latest RISC-V specification, including "G" ("IMAFD") standard instruction…
64-bit CPU with Modern RISC Architecture, MemBoost and PMA
The 64-bit AX27 is a 5-stage processor that supports the latest RISC-V specification, including “G“ (“IMAFD”) standard instructio…
High-performance 32-bit processor for real-time control
R807 utilizes an 8-stage pipeline and dual-issue out-of-order architecture.
Low power 32-bit processor with lightweight computing power
E804 utilizes a 3 to 4-stage variable-length pipeline and a scalar DSP computing engine, and can be optionally equipped with a fl…
Ultra-low power 32-bit processor resistant to physical damage
S802 utilizes a 2-stage minimalistic pipeline that provides nearly 20 special protection technologies for various invasive and no…
Ultra-low power processor with RISC-V architecture possessing secure execution capability
E902 utilizes a 2-stage minimalistic pipeline compatible with RISC-V architecture, and is enhanced in execution efficiency.
High performance, low power, 8-bit processor
The M8051EW and M8051W microcontroller cores are high performance versions of the popular 8051 8-bit microcontroller.
ColdFire V2 Core with AMBA peripherals connected in a subsytem
Building upon the 68K foundation, ColdFire offers RISC performance with industry- code density and a rich set of connectivity per…
64-bit RISC-V core with out-of-order pipeline based complex for Linux-based embedded systems
64-bit RISC-V core with out-of-order pipeline based complex.
32-bit Multiprocessor with Level-2 Cache-Coherence
AndesCore™ A25MP 32-bit multicore CPU IP is based on AndeStar™ V5 architecture.
Ultra Compact 32-bit RISC-V CPU Core
AndesCore™ N22 is a 32-bit 2-stage pipeline CPU IP core based on AndeStar™ V5 architecture for embedded applications that require…
Compact High-Speed 64-bit CPU Core
AndesCore™ NX25F is a compact 64-bit CPU IP core based on AndeStar™ V5 architecture which incorporated RISC-V technology, it is t…
High-performance 32-bit Superscalar Processor
C810 utilizes a 10-stage superscalar pipeline, with a standard memory management unit, and can run Linux and other operating syst…
Energy-efficient 32-bit superscalar processor
C807 utilizes an 8-stage pipeline and dual-issue superscalar architecture, with a standard memory management unit, and can run Li…