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Vendor:
Nuclei System Technology
Category:
CPU
32-Bit High Performance Processor - 2-Stage Pipeline, Single-issue
With extreme low area, N100 is a 32b RISC-V processor designed specifically for low power application.
Overview
With extreme low area, N100 is a 32b RISC-V processor designed specifically for low power application. N100 aims for cost sensitive application including IoT, MCU, sensor.
100 Series Performance and Configurability
| Nuclei CPU IP | N100 | ||
| Pipeline Stages | 2 | ||
| Issue-Width | Single-Issue | ||
| Hardware Multiplier | Configurable | ||
| Hardware Divider | Configurable | ||
| RISC-V ZC Extension | Configurable | ||
Key features
- Support RV32I/EMC/Zc ISA.
- 2-stage pipeline, extremely optimized micro-archtecture for low power and area.
- Configurable single cycle and multiple cycle Multiplier
- 32 Bits AHB-Lite system bus
- Configurable Divider
- Machine mode
- Configurable IRQC
- Full Standard Debug Function with JTAG/cJTAG port.
- Full Standard RISC-V Toolchain, and Linux/Windows IDE supported
Block Diagram
100 Series block diagram
Benefits
- Ultra-LowPower
- RV32I/EMC/Zc
- 2 Stage Pipeline
- Machine-Mode
- AHB-Lite
- Multiplier-divider
- RISC-V Standard Debug
- JTAG & cJTAG
- Low Latency Interrupt
- Full Development Toolkit
Specifications
Identity
Part Number
100 Series
Vendor
Nuclei System Technology
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
China
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Frequently asked questions about CPU IP cores
What is 32-Bit High Performance Processor - 2-Stage Pipeline, Single-issue?
32-Bit High Performance Processor - 2-Stage Pipeline, Single-issue is a CPU IP core from Nuclei System Technology listed on Semi IP Hub.
How should engineers evaluate this CPU?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.