Hitting the Memory Wall:Why Cache Miss Tolerance Defines CPU Performance Now
This article shares our experience using Google’s FlatBuffers library as a memory subsystem stress test on the Andes AX46MPV RISC-V core.
Vendor:
Nuclei System Technology
Category:
CPU
32-Bit & 64-Bit High Performance Processor - 6-Stage Pipeline, Single-issue
600 Series processors include four different classes: N600 (32 bit), U600 (32 bit + MMU), NX600 (64 bit) and UX600 (64 bit + MMU).
Overview
600 Series processors include four different classes: N600 (32 bit), U600 (32 bit + MMU), NX600 (64 bit) and UX600 (64 bit + MMU). With MMU, UX600 supports heavyload operating systems such as Linux. 600 Series can be applied to edge computing, data center, networking, etc.
Key features
600 Series Single Core Features
- RISC-V RV32 IMACFDBPKVZfh/Zcxlcz and RV64 IMACFDPBKVZfh/Zc ISA supported
- Dual Issue, in-order 6 stage Harvard Pipeline
- 64-bit AXI system bus, configurable 32-bit AHB-Lite slave port
- Double, Single and Half-Precision floating point
- Configurable SIMD DSP Extension
- Full Vector Extension with 128-b VLEN
- Configurable ILM/DLM (Instruction Local Memory) with ECC
- Configurable ICachewith ECC
- Configurable DCache with ECC
- Configurable MMU supported (SV32/SV39/SV48)
- PMP and TEE supported to meet the system security requirement
- Full standard debug function with JTAG and cJTAG
- Full standard RISC-V toolchain with Linux\Windows IDE supported
600 series SMP Multi Core Features
- Dual-mode feature supported (Application Processor mode and Real-time Processor mode)
- Up to 16 SMP cores in one Cluster
- SoC Connectivity
- Configurable Cluster Memory Port(64/128/256/512-bit)
- Cluster Peripheral Ports support 32-bit AHB-Lite protocol
- Up to 16 IOCP (I/O Coherent Port) Ports supported
- Support Hardware Data Prefetching mechanism
- Cluster Cache
- Configurable Cluster Cache size
- Configurable Cacheline size（64Bytes）
- Configurable multi-cycle Tag RAM and Data RAM
- Support cacheline LOCK, FLUSH and INVAL operations
- 16-way associative
- Can be configured to Cluster Local Memory
Block Diagram
600 Series block diagram
Benefits
- Real-time Feature
- RV32 IMACFDBPKVZfh/Zcxlcz, RV64 IMACFDPBKVZfh/Zc
- 6 Stage Pipeline Dual-issue
- I/D Cache
- Security(PMP, TEE)
- SP/DP FPU
- NICE Extension
- AXI system bus
- RISC-V Standard Debug
- JTAG & 2-wire JTAG
- Low Latency Interrupt
- Full Dev Kit & SDK
Specifications
Identity
Part Number
600 Series
Vendor
Nuclei System Technology
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
China
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Frequently asked questions about CPU IP cores
What is 32-Bit & 64-Bit High Performance Processor - 6-Stage Pipeline, Single-issue?
32-Bit & 64-Bit High Performance Processor - 6-Stage Pipeline, Single-issue is a CPU IP core from Nuclei System Technology listed on Semi IP Hub.
How should engineers evaluate this CPU?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.
Can this semiconductor IP be compared with similar products?
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