Vendor: Sifive, Inc. Category: CPU

8-stage, dual-issue, highly efficient in-order pipeline compatible with the RISC-V RV64GCV ISA

The SiFive Performance P270 is an 8-stage, dual-issue, efficient in-order pipeline compatible with the RISC-V RV64GCV ISA.

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RISC-V View all specifications

Overview

The SiFive Performance P270 is an 8-stage, dual-issue, highly efficient in-order pipeline compatible with the RISC-V RV64GCV ISA. With full support for the RISC V Vector Extension v 1.0RC, and combined with the SiFive Recode utility, which translates existing SIMD software from popular legacy architectures to RISC-V Vector assembly code, the P270 is an ideal replacement for dated SIMD architectures.

Key features

  • 256-bit vector length processor
    • Variable length operations, up to 256-bits of data per cycle, with dynamic vector length configuration
    • Ideal balance of control and data parallel compute
  • Performance
    • 5.75 CoreMarks/MHz
    • 3.25 DMIPS/MHz
    • SpecINT 2K6 = 4.6
  • Scalar processing built from U7 series core
    • Multi-layer Caching support for optimum data movement
    • Stride Prefetcher
    • Virtual memory support, up to 48-bit addressing
  • High performance, flexible connectivity to SoC peripherals
  • Multi-core processor configuration with up to 4-cores
  • Implements RISC-V Vectors v1.0-rc version
  • Dual issue scalar unit runs concurrently with vector unit
  • Key vector unit attributes
    • VLEN = 256. DLEN = 128 (datapath width). ELEN = 64 (datatypes)
    • Separate memory and ALU pipelines for concurrent operation
    • Vector operations, decoded and Queued in Vector Unit for parallel operation of Scalar and Vector units
  • Vector ALU
    • 128b ALU can perform 2x64b, 4x32b, 8x16b, 16x8b ops/cycle
    • Integer and Floating point data types supported
  • Vector Loads/Stores are 128b/cycle
    • L2 cache treated as primary memory
    • Load from L1 cache, initiates L2 cache load in parallel, minimizing L1 cache miss impact

Block Diagram

Performance P200 block diagram

What’s Included?

  • RTL Evaluation
  • Test Bench RTL
  • Software Development Kit
  • FPGA Bitstream
  • Documentation

Specifications

Identity

Part Number
Performance P200
Vendor
Sifive, Inc.
Type
Silicon IP

Compute

CPU Architecture
RISC-V

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Sifive, Inc.
HQ: USA
Contact Sifive, Inc.

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Frequently asked questions about CPU IP cores

What is 8-stage, dual-issue, highly efficient in-order pipeline compatible with the RISC-V RV64GCV ISA?

8-stage, dual-issue, highly efficient in-order pipeline compatible with the RISC-V RV64GCV ISA is a CPU IP core from Sifive, Inc. listed on Semi IP Hub.

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