Hitting the Memory Wall:Why Cache Miss Tolerance Defines CPU Performance Now
This article shares our experience using Google’s FlatBuffers library as a memory subsystem stress test on the Andes AX46MPV RISC-V core.
Vendor:
Andes Technology Corp.
Category:
CPU
Compact, Secure and Performance Efficiency 32-bit RISC-V Core
AndesCore™ D23 is a 32-bit 3-stage pipeline CPU IP core based on AndeStar™ V5/V5e architecture for embedded applications with sma…
Overview
AndesCore™ D23 is a 32-bit 3-stage pipeline CPU IP core based on AndeStar™ V5/V5e architecture for embedded applications with small gate count, and some dual-issue ability. In addition to commonly used RISC-V I/EMAC, single/double precision FPU and DSP extensions, it supports the recently ratified ISA extensions such as B (bit manipulation), K (scalar cryptography), and CMO (cache management operations) as well as Zce draft (code size reduction). The D23 implements ePMP and sPMP to improve core security; PPMA for on-the-fly change of memory attributes; and Andes V5 extensions that include StackSafe™ (for hardware stack protection), CoDense™, PowerBrake and WFI/WFE. The D23 supports both four-wire and two-wire JTAG debug and instruction trace interface for software development. On the performance front, it deploys several configurable options such as dynamic branch prediction, caches and local memories, multiplier optimized for performance or area. Moreover, it comes with rich features to ease SoC integration such as CLIC and PLIC for interrupt handling; an AHB-Lite system bus and an AHB-Lite low-latency interface; an APB bus for CPU local peripherals, and an AHB-Lite local memory access port for external bus masters. Some of the features will be implemented in CPU revision update, details below.
Key features
- AndeStar™ V5/V5e Instruction Set Architecture (ISA)
- Andes extensions for performance and code size enhancements
- 3-stage pipeline optimized for gate count and efficiency
- 16/32-bit mixable instructions for code density
- Instruction and data caches to speed up accessing embedded or external flash memory
- Branch prediction to speed up control code
- Enhanced and Supervisor-mode Physical Memory Protection (ePMP and sPMP) to enhance core security
- Core-Local Interrupt Controller (CLIC) for fast response, interrupt prioritization and pre-emption and Platform-Level Interrupt Controller (PLIC) for a wide range of cores and system event scenarios
- Patented CoDense™ technology to compress program code on top of the 16-bit extension
- Instruction Trace Interface supports RISC-V Processor Trace v1.0
- StakeSafe™ hardware to measure stack size, and detect runtime overflow/underflow
- Programmable Physical Memory Attributes (PPMA) for setting memory attributes dynamically
- PowerBrake, WFI/WFE (Wait For Interrupt/Event) for power management on different occassions
Block Diagram
AndesCore™ D23 block diagram
Applications
- Sensor fusion
- Smart Home and Matter (standard)
- Small IoT devices
- Wearable devices
- Motor control
Specifications
Identity
Part Number
AndesCore™ D23
Vendor
Andes Technology Corp.
Type
Silicon IP
Compute
CPU Architecture
RISC-V
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
R.O.C
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Frequently asked questions about CPU IP cores
What is Compact, Secure and Performance Efficiency 32-bit RISC-V Core?
Compact, Secure and Performance Efficiency 32-bit RISC-V Core is a CPU IP core from Andes Technology Corp. listed on Semi IP Hub.
How should engineers evaluate this CPU?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.