S2C Named Andes Technology’s 2026 Partner of the Year
本月，头部数字EDA企业思尔芯宣布，荣获RISC-V处理器IP领导厂商Andes晶心科技（Andes Technology）颁发的“2026年度最佳合作伙伴”奖项。该荣誉旨在表彰思尔芯在RISC-V生态共建、原型验证平台支撑及联合市场拓展中与Andes晶心深度协同、持续创造客户价值的突出表现。
Vendor:
Andes Technology Corp.
Category:
CPU
RISC-V CPU IP With ISO 26262 Automotive Functional Safety Compliant
AndesCore™ N25F-SE is a 32-bit CPU IP core that supports ISO 26262 ASIL B level functional safety for automotive applications.
Overview
AndesCore™ N25F-SE is a 32-bit CPU IP core that supports ISO 26262 ASIL B level functional safety for automotive applications. Approved based on the functional safety assignments of a Safety Element Out-of-Context (SEooC), which includes the ISO 26262 compliant development process and the qualitative approach with respect to hardware safety analysis, N25F-SE is certified to be used in safety-related applications.
Based on AndeStar™ V5 architecture that incorporated RISC-V technology, N25F-SE is capable of delivering high per-MHz performance and operating at high frequencies with small gate count. It supports single and double precision floating point instructions, branch prediction for efficient branch execution, Instruction and Data caches, local memories for low-latency accesses, and ECC for memory error protection. Features also includes RISC-V Platform Level Interrupt Controller, AXI 64-bit or AHB 64/32-bit system bus, WFI mode for low power and power management, and JTAG debug interface.
Functional Safety
- For general-purpose control of embedded systems in automotive applications
- Compliant with ISO 26262:2018 standard parts 2, 4, 5, 8 and 9 for ASIL (Automotive Safety Integrity Level) B
- Independent assessment and certification by SGS-TÜV Saar GmbH
- AndesCore™ N25F-SE ISO 26262 compliant certificate
Key features
- AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
- Floating point extensions
- Bit-manipulation extensions
- Andes extensions, architected for performance and functionality enhancements
- 32-bit, 5-stage pipeline CPU architecture
- 16/32-bit mixable instruction format for compacting code density
- Branch prediction to speed up control code
- Return Address Stack (RAS) to speed up procedure returns
- Physical Memory Protection (PMP)
- Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting wide range of system event scenarios
- Interrupt handling for real-time performance
- Patented CoDense™ technology to further reduce code size
Block Diagram
AndesCore™ N25F-SE block diagram
Applications
- Networking and Communications
- Advanced Driver-Assistance Systems
- Video and Image Processing
- Storage and Media Streaming
Specifications
Identity
Part Number
AndesCore™ N25F-SE
Vendor
Andes Technology Corp.
Type
Silicon IP
Compute
CPU Architecture
RISC-V
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
R.O.C
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Frequently asked questions about CPU IP cores
What is RISC-V CPU IP With ISO 26262 Automotive Functional Safety Compliant?
RISC-V CPU IP With ISO 26262 Automotive Functional Safety Compliant is a CPU IP core from Andes Technology Corp. listed on Semi IP Hub.
How should engineers evaluate this CPU?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.