CPU IP cores provide general-purpose processing for application, control, and system software workloads in modern SoC and ASIC designs.
These IP cores deliver programmable compute for embedded and high-performance SoCs, often serving as the central control or application processor in the architecture
This catalog allows you to compare CPU IP cores from leading vendors based on performance, power efficiency, software ecosystem, and process node compatibility.
Whether you are designing application processors, embedded systems, networking equipment, or compute SoCs, you can find the right CPU IP for your application.
32-Bit & 64-Bit High Performance Processor - 9-Stage Pipeline, Dual-issue
900 Series processors include four different classes: N900 (32 bit), U900 (32 bit + MMU), NX900 (64 bit) and UX900 (64 bit + MMU).
32-Bit High Efficiency Processor - 3-Stage Pipeline, Single/Dual-issue
N300 Series is a 32-bit RISC-V processor designed for applications requiring extreme energy efficiency and DSP/FPU features.
32-Bit Low Power Processor - 2-Stage Pipeline, Single-issue
N200 Series is designed for deeply embedded application with low power and area consumption.
RVA23, Multi-cluster, Hypervisor and Android
AndesCore™ AX66 64-bit multicore CPU IP is a high-performance quad decode 13-stage superscalar out-of-order processor based on An…
64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
AndesCore™ AX46MP(V) 64-bit multicore CPU IP is an 8-stage superscalar processor with Vector Processing Unit (VPU) based on AndeS…
32 bit RISC-V Multicore Processor with 256-bit VLEN and AMM
AndesCore™ A46MP(V) 32-bit multicore CPU IP is an 8-stage superscalar processor with Vector Processing Unit (VPU) based on AndeSt…
32-bit Multiprocessors with Level-2 Cache-Coherence
AndesCore™ A45MP 32-bit multicore CPU IP is an 8-stage superscalar processor based on AndeStar™ V5 architecture.
Highly configurable HW PQC acceleration with RISC-V processor for full CPU offload
configurable HW PQC acceleration with RISC-V processor for full CPU offload, configurable as Subsystem or RoT, with SCA and FIA p…
The ARC-V™ RMX-100 series processors are optimized for use in embedded applications where power and area are the utmost concern.
The ARC-V™ RMX-500 Processors are based on the RISC-V instruction set architecture (ISA) and optimized for use in embedded applic…
ARC-V RMX Series Functional Safety Processor IP
The ARC-V™ RMX-110-FS and RMX-510-FS Functional Safety Processors simplify development of safety-critical applications and accele…
Centralised Real Time Processor IP Core
We provide many configurations for our cryptographic solutions based on the requirements of the project.
A CPU Foundation for the Automotive Industry The Arm Neoverse V3AE CPU is built to deliver maximum performance for automotive app…
Neoverse Compute Subsystems N3 (CSS N3)
The Performance-per-Watt Arm Neoverse N3 Platform Validated by Arm for Networking and Edge Markets configurable to target 5G, DPU…
Neoverse Compute Subsystems V3 (CSS V3)
The High-Performance Arm V3 Platform Performance-Optimized and Validated by Arm Arm Neoverse CSS V3 is the fastest path to buildi…
64-bit RISC-V high-performance embedded core
64-bit RISC-V high-performance embedded core.
32-bit RISC-V compact high-performance embedded core
32-bit RISC-V compact high-performance embedded core.
64-bit RISC-V core with in-order dual issue pipeline based complex for Linux-based systems
64-bit RISC-V core with in-order dual issue pipeline based complex.
Superscalar Out-of-Order Execution Multicore Cluster
AndesCore™ AX65 64-bit multicore CPU IP is a high-performance quad decode 13-stage superscalar out-of-order processor based on An…
Compact and Performance Efficiency 32-bit RISC-V Core
The AndesCore™ N225 is a 32-bit 3-stage pipeline CPU IP core based on AndeStar™ V5 architecture for embedded applications with sm…