Overview
The SiFive Automotive™ E6-A series is designed for a variety of real-time, 32-bit applications, from system control to hardware security modules (HSMs) and safety islands, and of course for use as standalone in microcontrollers.
A mid-range power efficient performance 32-bit embedded processor that is fully-compliant with the RISC-V ISA. Its advanced memory subsystem enables inclusion of tightly-integrated memory and caches.
SiFive Automotive
SiFive Automotive™ solutions address automotive needs for current and future applications like infotainment, cockpit, connectivity, ADAS, and electrification as the automotive market transitions to zonal architectures and manufacturers are asking for the energy efficiency, simplicity, security, and software flexibility that RISC-V offers.
SiFive Automotive E6-A Features
The SiFive Automotive E6-A Series is a 32-bit RISC-V processor family, fully optimized for area, performance, and efficiency, specifically designed for the Automotive and Functional Safety markets. Building on the robust foundations of the mature SiFive Essential™ portfolio, the multi-core capable design of the E6-A Series offers industry best-in-class functional safety support as a Safety Element out of Context to enable use in applications with Automotive Safety Integrity Level (as per ISO26262) up to ASIL B and ASIL D.
The E6-AB, targeted at ASIL B integrity levels, employs minimal hardware redundancy of the logic to guarantee safety metrics are satisfied, without the use of Software Test Libraries (STL), enabling faster time to market and minimizing software integration work.
The finely tuned combination of out-of-the-box features and design scalability ensures designers can achieve the optimal balance of power, performance, and area while achieving the fastest time to market for the automotive microcontrollers, system controllers, battery management systems (BMS), and safety island for SoC markets. In addition to the automotive market, the E6-A series is also an ideal choice for broader deployment in microcontroller applications requiring functional safety capabilities.
Learn more about CPU IP core
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In this blog, I dive a little deeper into the options to efficiently couple a processor from the X100 series to a hardware accelerator.
When I joined SiFive in early 2024, the initial focus (which has since broadened) was to explore how best to drive adoption of SiFive’s RISC-V technology into system-on-chip components targeting data center use cases.
Reflecting on how far we’ve come since SiFive launched the world’s first RISC-V development boards back in 2016, it’s clear we’ve been on an incredible journey together with the RISC-V software community.
