Vendor: TurboConcept Category: Channel Coding

DVB-S2X FEC encoder

The Core can reach payload bitrates up to 2.5 Gbits/s ( equivalent baud rates > 600Mbaud).

Overview

The Core can reach payload bitrates up to 2.5 Gbits/s ( equivalent baud rates > 600Mbaud). The Core implements a very efficient parallel architecture for BCH and LDPC processing. It is fully validated and available on FPGA and ASIC targets.

Key features

  • Functional specifications:
    • Fully compliant with DVB-S2 and DVB-S2X specifications
    • Modulations: QPSK, 8PSK, 16APSK, 32APSK, 64APSK, 128APSK and 256APSK
    • Supports CCM, VCM, ACM modes
    • Covers BCH and LDPC encoding, block interleaver and I/Q symbol mapper
  • Core features:
    • Payload bitrate up to 2.5 Gbps payload
    • Baud rate up to 620 Mbaud
    • Advanced architecture allowing parallelized BCH and LDPC encoding
    • Optimized footprint in FPGA and ASIC
    • Frame-by-frame on-the-fly configuration
    • Symbol-level back pressure
    • AXI-stream interfaces

Applications

  • DVB-S2
  • DVB-S2X
  • Governmental
  • Backhauling

Specifications

Identity

Part Number
TC4050
Vendor
TurboConcept
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

TurboConcept
HQ: FRANCE

Learn more about Channel Coding IP core

Frequently asked questions about Channel Coding IP cores

What is DVB-S2X FEC encoder?

DVB-S2X FEC encoder is a Channel Coding IP core from TurboConcept listed on Semi IP Hub.

How should engineers evaluate this Channel Coding?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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