Vendor: Continuous-bits Ltd. Category: Channel Coding

ASIC IP-core for high-throughput decoding of DVB-S2/S2X, and DVB-RCS/RCS2

Very high throughput (several Gbps) decoder that can be configured on-the-fly as: DVB-S2/S2X LDPC decoder or as Six independent D…

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Overview

Very high throughput (several Gbps) decoder that can be configured on-the-fly as:
DVB-S2/S2X LDPC decoder
or as
Six independent DVB-RCS/RCS2 Turbo decoders
 

Key features

  • On-the-fly configuration, with each codeword:
  • (a) LDPC/Turbo
  • (b) All DVB-S2/S2X code rate (including Low-SNR)
  • (c) Turbo interleaver parameters and codeword length per RCS/RCS2 decoder
  • (d) Maximal number of iterations.
  • 500MHz clock with RAD-hard cells (TSMC 65LP)
  • Belief-propagation iterative decoding (floating-point performance)
  • Single-port memories, external to the IP-core
  • Options for synchronous or asynchronous reset
  • Efficient HW utilization
  • Indications on the number iterations done, early-convergence,
  • and SNR
  • Low power design:
  • (a) Gated-clock registers and FF
  • (b) All memories cs port is negated on clocks not used to access the memory
  • (c) Continuous monitoring of convergence enables early stop of iterations when a codeword is found, or earlier if instructed due to system
  • considerations.
  • (d) idle signal enables powering- offthe whole IP-core
  • Single clock synchronous design
  • All IP-core inputs and outputs are registered
  • Portable to all ASIC and FPGA technologies

What’s Included?

  • 1) Simulation bit-exact shared-object for Matlab/Octave/C/Cpp
  • 2) Synthesizable Verilog HDL code
  • 3) HDL test bench with vectors
  • 4) Integration guidelines and datasheet
  • 5) Support

Specifications

Identity

Part Number
Cb-DVB-S2X-RCS2
Vendor
Continuous-bits Ltd.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Continuous-bits Ltd.

Learn more about Channel Coding IP core

Practical Considerations of LDPC Decoder Design in Communications Systems

This paper covers some practical aspects of designing the LDPC decoder starting from comparison between different techniques, different decoders parameters or standards, the effect of those parameters on the LDPC performance, also it discusses the algorithm selection process, and floating point implementation process.

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Frequently asked questions about Channel Coding IP cores

What is ASIC IP-core for high-throughput decoding of DVB-S2/S2X, and DVB-RCS/RCS2?

ASIC IP-core for high-throughput decoding of DVB-S2/S2X, and DVB-RCS/RCS2 is a Channel Coding IP core from Continuous-bits Ltd. listed on Semi IP Hub.

How should engineers evaluate this Channel Coding?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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