10G I.3 BCH Encoder/Decoder for ITU G.975.1
The IPrium-10G-I.3-BCH-Codec IP core implements "Concatenated BCH super FEC" with BCH(3860, 3824) and BCH(2040, 1930) forward err…
Overview
The IPrium-10G-I.3-BCH-Codec IP core implements "Concatenated BCH super FEC" with BCH(3860, 3824) and BCH(2040, 1930) forward error correction algorithms for optical lines and is fully compatible with ITU-T G.975.1 (super-FEC for 2.5G, 10G and 40G optical networks).
Key features
- Fully synchronous design, using single clock
- Fully synthesizable drop-in module for FPGAs
- Optimized for high performance and low resources
- Low implementation loss
- Fully verified and real-time tested on a FPGA based development platform
- Considerations for easy ASIC integration
- Validated on IPrium Evaluation Boards
What’s Included?
- VQM/NGC/EDIF netlists for Altera Quartus II, Xilinx ISE, Lattice Diamond or Microsemi (Actel) Libero SoC
- IP Core testbench scripts
- Design examples for Altera, Xilinx, Lattice, and Microsemi (Actel) evaluation boards
- Free 1 year warranty and support period
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about Channel Coding IP cores
What is 10G I.3 BCH Encoder/Decoder for ITU G.975.1?
10G I.3 BCH Encoder/Decoder for ITU G.975.1 is a Channel Coding IP core from IPrium LLC listed on Semi IP Hub.
How should engineers evaluate this Channel Coding?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.