Vendor: Small World Communications Category: Channel Coding

16 State DVB-S2/DVB-S2X Tail Biting Viterbi Decoder

The VA04D is a 16 state tail-biting error control decoder using the maximum likelihood Viterbi algorithm.

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Overview

The VA04D is a 16 state tail-biting error control decoder using the maximum likelihood Viterbi algorithm. The decoder is designed to decode the DVB-S2 or DVB-S2X standard rate 1/5 tail biting convolutional code.

Key features

  • 16 state (memory m = 4, constraint length 5) tail biting Viterbi decoder
  • Rate 1/5 (inputs can be punctured for higher rates)
  • Optional or standard DVB-S2/DVB-S2X code polynomials
  • Data length K from 4 to 32 bits
  • Up to 382 MHz internal clock
  • Up to 46 Mbit/s decoding speed (K = 16)
  • 6-bit received signed magnitude data
  • 1315 6-input LUTs
  • Asynchronous logic free design
  • Free simulation software
  • Available as VHDL core for Xilinx FPGAs under SignOnce IP License. ASIC, Altera, Lattice and Microsemi cores available on request.

What’s Included?

  • All Licenses
    • Xilinx VHDL Core
    • Test vector generator
  • ASIC License
    • VHDL ASIC Core
    • C++ bit/cycle exact simulation model

Specifications

Identity

Part Number
VA04D
Vendor
Small World Communications
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Small World Communications

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Frequently asked questions about Channel Coding IP cores

What is 16 State DVB-S2/DVB-S2X Tail Biting Viterbi Decoder?

16 State DVB-S2/DVB-S2X Tail Biting Viterbi Decoder is a Channel Coding IP core from Small World Communications listed on Semi IP Hub.

How should engineers evaluate this Channel Coding?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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