Overview
10G Unmanaged Ethernet Switch IP core (10G UES) is an evolution of our 1G Unmanaged Ethernet Switch IP Core (UES). The 10G UES implements a plug-and-play Ethernet switch for reconfigurable devices. It does not require external configuration and it has been designed to address the maximum throughput using the minimum resources.
The 10G Unmanaged switch IP implements a non-blocking crossbar matrix that allows wire-speed communication among all the ports. The IP Core buffers and verifies each frame before forwarding it. Nevertheless, the latency time has been minimized to nanoseconds order. Furthermore, the switch IP Core supports IEEE 1588 V2 Transparent Clock functionalities. This feature, corrects PTP frames introducing the error generated by the switch, allows the interconnection of IEEE 1588 synchronized devices maintaining the highest levels of accuracy.
10G Unmanaged Switch IP Core is the perfect Ethernet Switch IP to implement Ethernet based Industrial Networks. It provides MII/GMII/RGMII native interfaces for Ethernet PHY devices and it can be combined with Xilinx Ethernet 1G/2.5G BASE-X PCS/PMA, it can support RMII or SGMII among other interfaces. It also supports and AXI4-Stream interface to be connected to other IP Cores that do not feature MAC based interfaces.
10G Unmanaged Switch can be supported on the following Xilinx FPGA Families:
* 6-Series (Spartan, Virtex)
* 7-Series (Zynq, Spartan, Artix, Kintex, Virtex)
* Ultrascale (Kintex, Virtex)
* Ultrascale+ (Zynq MPSoC, Kintex, Virtex)
Learn more about Ethernet IP core
Crius uses SOC-Eâs PreciseTimeBasic (PTB) IP core to implement the IEEE 1588 slave function, with a hardware timestamping unit inserted between the MAC and PHY layers so that PTP event messages are timestamped in logic rather than in software.
