Simulation VIP for Ethernet UEC

Best-in-class Ethernet Verification IP for your IP, SoC, and System-level Design Testing

The Cadence Verification IP (VIP) for Ethernet UEC provides a mature, highly capable compliance verification solution for the Ultra Ethernet protocols stack, incorporating bus functional model (BFM) and integrated protocol checkers and coverage. The VIP for Ultra Ethernet is designed for easy integration in test benches at IP, system-on-chip (SoC), and system levels, helping to reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP for Ultra Ethernet is compatible with the industry-standard Universal Verification Methodology (UVM) and runs on all leading simulators.

UEC is a family of protocols primarily of the data link layer and a couple of layers above it in the OSI Communication model, which delivers the ultra-low latency and high bandwidth necessary to connect a million nodes building a massive AI scale-out network and provides the interoperability and full communication stack architecture. These protocols are usually designed to work over a framework of Ethernet MAC and PHY layers.

Supported specifications: UEC-LLR Specification v0.82.

The following table shows key features from the specifications that are implemented in the VIP:

• Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
• Callbacks access at multiple TX and RX queue points for scoreboarding, data manipulation, and error injection
• Transaction Tracker: Configurable tracking of all the transactions on the channels
• SystemVerilog coverage infrastructure for extendable coverage
• Predefined protocol checkers to evaluate the compliance of the DUT model to protocol requirements