SOC-E IP Cores

Implements an IEEE1588-2008 (Version 2) PTP slave / time receiver clock for FPGA

• IEEE-1588 / PTP

Multi-port, multi-rate managed Ethernet switch with Time-Sensitive Networking (TSN) capabilities

• Ethernet

Multi-port, multi-rate managed ethernet switch with a rich set of layer-2 configurable features

• Ethernet

Provides Time-Sensitive Networking (TSN) capabilities to devices that operate as end systems in the network

• Ethernet

Provides sub-microsecond time synchronization, ensuring maximum flexibility for every scenario

• IEEE-1588 / PTP

IRIG 200-04 compliant time synchronization slave / time receiver for FPGA

• IEEE-1588 / PTP

IRIGtimeM implements an IRIG 200-04 compliant time synchronization master on FPGA devices.

• IEEE-1588 / PTP

Provides nanosecond level clock synchronized to network PTP time transmitter.

• IEEE-1588 / PTP

HSR/PRP redundancy + Legacy ethernet ports

• Ethernet

Multi-port, multi-rate managed Ethernet switch with Time-Sensitive Networking (TSN) capabilities

• Ethernet

High-availability Seamless Redundancy and Parallel Redundancy Protocol (HSR and PRP, IEC 62439-3 Clause 5 and 4 respectively) Edition 4.0 protocols

• Ethernet

Complete, reliable and fast SpaceWire encoder-decoder which has been designed according to ECSS-E-ST-50-12C.

• Spacewire

The demand for higher bandwidth in the car is growing quickly.

• Ethernet

IEC 61850/62351 Substation Automation Systems Cryptographic (SASCrypt) IP Core secures the strict real-time traffic used in the S…

• Symmetric Crypto

Unmanaged Ethernet Switch IP core (UES) implements a plug-and-play Ethernet switch on reconfi gurable devices.

• Ethernet

The SoC-e PROFINET Switch IP core is an Intellectual Property (IP) Core for FPGAs.

• Ethernet

10G Unmanaged Ethernet Switch IP core (10G UES) is an evolution of our 1G Unmanaged Ethernet Switch IP Core (UES).

• Ethernet

Configuration-over-Ethernet (COE) is a Layer 2 configuration protocol design by SoC-e to access remotely to FPGAs that implements…

• Ethernet