VESA Display Stream Compression (DSC) IP Core
Bitec
•
HQ:
Spain
Display Stream Compression offers inter-operable, visually lossless real-time, video compression to satisfy the emerging high ban…
- VESA DSC
Compare 423 Multimedia Interface IP Cores from 50 vendors
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Display Stream Compression (DSC 1.2) Decoder
Trilinear Technologies, Inc.• HQ: USAThe Display Stream Compression (DSC) Decoder core offers realtime decompression of high-definition streams with resolutions from …
- VESA DSC
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CSI2 RX; Camera Serial Interface, MIPI Compliant
HCL Technologies• HQ: IndiaThe CSI2 Receiver IP Interfaces between Camera module which has the transmitter and the application processor.
- MIPI
- Now
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FPD LVDS Display Interface, 1 Port / 2 Port LCD Panel
Digital Blocks, Inc.• HQ: USAThe DB-FPD-LVDS-TX LVDS Display Interface IP Core interfaces parallel 18-bit/24-bit RGB Pixel Data with display timing VSYNC, HSY…
- V-By-One
- Successful in Company FPGA Kit Demo Reference Design, Customer Products
- Immediately
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T2M GmbH• HQ: Germany
HDMI Receiver Link IP Core supporting the standard of HDMI 1.3a, which will be quickly implemented into SoC of consumers; product…
- HDMI
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Rambus, Inc.• HQ: USA
The MIPI DSI-2 controller core is optimized for high performance, low power and small size.
- MIPI
- Now
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Rambus, Inc.• HQ: USA
The MIPI CSI-2 controller core is optimized for high performance, low power and small size.
- MIPI
- Now
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DisplayPort (DP) 1.4a / Embedded DisplayPort (eDP) 1.4a RX PHY
VeriSilicon Microelectronics (Shanghai) Co., Ltd.• HQ: USAThe DP/eDP Combo RX PHY IP is compliant to the DisplayPort v1.4a and embedded DisplayPort v1.4a.
- PHY
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DisplayPort (DP) 1.4a / Embedded DisplayPort (eDP) 1.4a TX PHY
VeriSilicon Microelectronics (Shanghai) Co., Ltd.• HQ: USAThe DP/eDP Combo TX PHY IP is compliant to the DisplayPort v1.4a and embedded DisplayPort v1.4a.
- PHY
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VeriSilicon Microelectronics (Shanghai) Co., Ltd.• HQ: USA
HDMI RX PHY is the physical layer of a single-port HDMI transmitter interface.
- PHY
- HDMI
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VeriSilicon Microelectronics (Shanghai) Co., Ltd.• HQ: USA
HDMI TX PHY is the physical layer of a single-link HDMI transmitter interface.
- PHY
- HDMI
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VeriSilicon Microelectronics (Shanghai) Co., Ltd.• HQ: USA
VBO Receiver with four and eight lanes for video communication
- PHY
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VeriSilicon Microelectronics (Shanghai) Co., Ltd.• HQ: USA
VBO Transmitter with 8 lanes and 16 lanes for video communication
- PHY
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RISC-V Display Connectivity Subsystem (DCS)
Trilinear Technologies, Inc.• HQ: USAModern display links have evolved into complex communication systems requiring continuous management of authentication, topology,…
- Displayport
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Arasan Chip Systems Inc.• HQ: USA
The SWI3S (SoundWire I3S Interface) Manager Controller Core IP implements the link protocol to communicate in half-duplex fashion…
- MIPI
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InPsy• HQ: Taiwan (R.O.C.)
The DisplayPort 1.4 Transmitter PHY is for transmitting high-definition video and audio, making it an ideal choice for a wide ran…
- Displayport
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Trilinear Technologies, Inc.• HQ: USA
The DisplayPort Link Policy Maker (LPM) is a DisplayPort 1.4/2.0 compliant software stack that manages and controls the DisplayPo…
- Displayport
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MIPI - Enables high-speed, low-power data transfer for displays and cameras
XtremeSilica• HQ: IndiaMIPI (Mobile Industry Processor Interface) is a high-speed, low-power interface designed for video and imaging applications in mo…
- MIPI
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HDMI - Ensures seamless video and audio transmission with HDMI standards
XtremeSilica• HQ: IndiaHDMI Verification IP validates HDMI controller functionality in SoC designs, ensuring compliance with HDMI standards like 1.4, 2.…
- HDMI
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DisplayPort - Validates high-quality video and audio transmission for displays
XtremeSilica• HQ: IndiaDisplayPort is a high-performance digital display interface designed for connecting computers, monitors, and other video devices.
- Displayport