The XC21 is the most efficient vector DSP core available today for communications applications.
- DSP Core
Discover DSP and Math IP for digital signal processing, arithmetic acceleration, and compute-intensive algorithms in semiconductor designs. This category includes IP cores optimized for filtering, transforms, vector processing, fixed-point and floating-point computation, and real-time signal manipulation.
Compare DSP and Math IP by processing architecture, supported numeric formats, throughput, latency, programmability, power efficiency, and target application. These IP solutions are widely used in communications, audio, vision, radar, industrial control, AI preprocessing, and embedded compute platforms.
The XC21 is the most efficient vector DSP core available today for communications applications.
Nand Flash write cycles are limited.
LDPC (1723,2048) core is compliant with IEEE Standard 802.3.2018 Ethernet specification.
FEC RS (544,514) core is compliant with standard CPRI 7.0 Specification, IEEE Standard 802.3.2018 Ethernet specification and JESD…
FEC RS (528,514) core is compliant with standard CPRI 7.0 Specification, IEEE Standard 802.3.2018 Ethernet specification and JESD…
FEC RS (255,251) core is compliant with standard HDMI 2.1/2.1a and Scalabale Low Voltage Signaling with Embedded Clock (SLVS_EC) …
FEC RS (254,250) core is compliant with standard VESA Display Port version 1.4/2.0/2.1.
FEC RS (198,194) core is compliant with standard Universal Serial Bus 4 Specification and standard VESA Display Port version 2.0/…
The FPU Verification IP provides an effective & efficient way to verify the components interfacing with FPU interface with a RISC…
High-performance AI dataflow processor with scalable vector compute capabilities
The new XM Series offers an extremely scalable and efficient AI compute engine.
LDPC Decoder for 5G NR and Wireless
The 5G NR LDPC Decoder IP Core offers a robust solution for LDPC decoding, featuring a dedicated LDPC decoder block for optimal p…
Wide range of dedicated, high performance, low latency RS FEC IP cores to meet any error correction requirement The Reed Solomon …
Vision DSP built using 128-bit SIMD and offering up to 0.4 TOPS of performance
Built using 1024-bit SIMD and offering up to 3.84TOPS of performance The Cadence® Tensilica® Vision Q8 DSP delivers up to 3.84 te…
Cache-Coherent HiFi 5s Symmetric Multiprocessor
Efficient 32-bit processing for audio enhancement algorithms, wideband voice codecs, and multi-channel audio The Cadence® Tensili…
PUSCH Equalizer for 3GPP 5G NR
3GPP compliant equalisation, double uplink performance and spectral efficiency with this 5G NR Uplink Physical Shared Channel sol…
DisplayPort 1.4 FEC Transmitter (Tx) ASIL-B
The DisplayPort Forward Error Correction (FEC) Transmitter IP Core implements Reed-Solomon FEC and symbol interleaving as specifi…
CYB-RS-en core implements the Reed Solomon encoding algorithm and is parameterized in terms of bits per symbol, maximum codeword …
CYB-RS-de core implements the Reed Solomon decoding algorithm and is parameterized in terms of bits per symbol, maximum codeword …
The Reed Solomon Encoder is fed with an input message of K information symbols, the Encoder appends 2T parity symbols to the inpu…
VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
The DisplayPort Forward Error Correction (FEC) Transmitter IP core implements Reed-Solomon FEC and symbol interleaving as specifi…