The DVB-S2-LDPC-BCH block is a FEC (Forward Error Correction) subsystem for Digital Video Broadcasting via Satellite.
- Channel Coding
- In Production
- Immediate
- yes
Discover DSP and Math IP for digital signal processing, arithmetic acceleration, and compute-intensive algorithms in semiconductor designs. This category includes IP cores optimized for filtering, transforms, vector processing, fixed-point and floating-point computation, and real-time signal manipulation.
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The DVB-S2-LDPC-BCH block is a FEC (Forward Error Correction) subsystem for Digital Video Broadcasting via Satellite.
Analog TV Demodulator and Decoder IP (Silicon Proven)
The Analog TV Demodulator and Decoder IP core is extracted from a production chip and a silicon-proven IP core.
DVB-S2X WideBand Demodulator IP
This is a high-performance, dual high-symbol-rate (HSR) DVB-S2/S2X demodulator IP extarcted from production chipsets with integra…
DVB-S2X WideBand Demodulator & Decoder IP (Silicon Proven)
This is a high-performance, dual high-symbol-rate (HSR) DVB-S2/S2X demodulator IP extarcted from production chipsets with integra…
CCSDS SCCC Turbo Encoder and Decoder
The recommended CCSDS 131.2-B-1 standard introduces a Serial Concatenated Convolutional Code (SCCC).
DVB-S2/S Demodulator and Decoder IP (Silicon Proven)
The DVB-S2/S Demodulator IP core is a silicon-proven IP core extracted from Production chips.
The DVB-RCS2 modulator is a low-complexity high-performance solution that allows for symbol rates of up to 160 MSymb/s on FPGAs.
Floating-point (IEEE 754) IP based on Arria 10 and Stratix 10 FPGAs
This circuit uses Altera’s new Arria and Stratix 10 FPGAs with hardwired support for floating-point operations (IEEE754).
DVB-S2X Wideband BCH and LDPC Decoder
The DVB-S2X wideband decoder is a silicon-proven, scalable solution that allows for symbol rates of up to 500 Msymb/s on FPGAs.
The DVB-S2X wideband modulator is a low-complexity high-performance solution that allows for symbol rates of up to 500 MSymb/s (4…
The DVB-S2X Wideband demodulator is a low-complexity high-performance solution that allows for symbol rates of up to 500 MSymb/s …
FlexDPD is a mature, flexible and solution for the linearization of RF Power Amplifiers (PA).
DisplayPort 1.4 FEC Receiver (Rx)
The DisplayPort Forward Error Correction (FEC) Receiver IP core implements Reed-Solomon FEC and symbol interleaving as specified …
Fully Configurable LDPC Encoder
In channel coding redundancy is inserted in the transmitted information bit-stream.
Programmable OFDM Channel Estimator
The wideband OFDM signal suffers from frequency selective fading.
The DVB-S2X modulator is a low-complexity high-performance solution that allows for symbol rates of up to 250 MSymb/s (2 Gbit/s f…
PMCC_XCM_64x64_D IP block is a low-power array of 1GHz clocked Cross-Correlator cells that are synchronously acquiring two sets o…
Cross-Correlator With 64x2 Channels
PMCC_XCM_64x64 is an IP block capable of calculating the cross-correlations between 64x2 analog signals supplied to the inputs AR…
DOCSIS 3.1 LDPC Decoder (PLC / NCP / Data)
Data Over Cable Service Interface Specification (DOCSIS) is an international telecommunications standard that permits the additio…
Chroma Re-sampler core can be used as chroma sub sampling or chroma up sampling.