Discover DSP and Math IP for digital signal processing, arithmetic acceleration, and compute-intensive algorithms in semiconductor designs. This category includes IP cores optimized for filtering, transforms, vector processing, fixed-point and floating-point computation, and real-time signal manipulation.
Compare DSP and Math IP by processing architecture, supported numeric formats, throughput, latency, programmability, power efficiency, and target application. These IP solutions are widely used in communications, audio, vision, radar, industrial control, AI preprocessing, and embedded compute platforms.
ITU 25G PON LDPC Encoder and Decoder
The common transmission convergence (ComTC) layer for Higher Speed Passive Optical Networks is defined as part of the FEC in the …
LDPC Encoder/Decoder for Flash controller
The LDPC IP is a Low-density parity-check code encoder and decoder designed for 3D NAND Flash error correction to address the rel…
3GPP compliant coding and modulation for Downlink Physical Shared Channels The Physical Downlink Shared Channel (PDSCH) is used f…
CCSDS 131.2 Wideband Demodulator
The Creonic CCSDS high performance wideband demodulator performs all tasks of an inner receiver.
3.5 to 5 GHz, 7 to 10 GHz and 14 to 20 GHz FMCW Modulator for RADAR
The WEA520SFMCW22G is an ultra-fast ultra-linear FMCW frequency synthesizer capable of generating 1400 MHz Chirps at 20 GHz frequ…
IEEE 802.11 n/ac/ax LDPC Decoder
The Low Density Parity Check (LDPC) codes are , capacity approaching channel codes and have exceptional error correction capabili…
IEEE 802.11 n/ac/ax LDPC Encoder
The Low Density Parity Check (LDPC) codes are , capacity approaching channel codes and have exceptional error correction capabili…
DVB-RCS2 Multi-Carrier Receiver
DVB-RCS2 (Digital Video Broadcast – Second Generation DVB Interactive Satellite System) is the latest ETSI standard of the second…
High performance dual-issue, out-of-order, 7-stage Vector processor (DSP) IP
World's first audio DSP IP with RISC-V Vector processor architecture RiVAI-V1 is a dual-issue, Out-of-Order execution, 7-stage pi…
This is an LDPC decoder compliant with the IEEE 802.11 n/ac/ax standards.
IEEE802.11n/ac/ax Wi-Fi LDPC Decoder and Encoder
The 802.11n/ac/ax LDPC decoder is developed for high throughput WLAN applications.
DVB-S2 LDPC BCH Decoder and Encoder
The DVB-S2 LDPC-BCH block is a FEC (Forward Error Correction) subsystem for Digital Video Broadcasting via Satellite.
The DVB-S2X LDPC Decoder is a FEC core decoder for Digital Video Broadcasting via Satellite.
3GPP compliant coding and modulation for Physical Shared Channels The Physical Uplink Shared Channel (PUSCH) is used to for uplin…
DVB-C Demodulator IP (Silicon Proven)
The DVB-C Demodulator IP core is a silicon-proven IP core and extracted from the production chip, It is a QAM (quadrature amplitu…
DVB-T2/T Demodulator and Decoder IP (Silicon Proven)
The DVB-T2/T IP is a silicon-proven IP core extracted from a production chip contains FEC.
CCSDS 231.0 LDPC Encoder and Decoder
The CCSDS 231.0 LDPC IP supports the LDPC coding schemes as defined by the CCSDS standard.
The DVB-S2-LDPC-BCH block is a FEC (Forward Error Correction) subsystem for Digital Video Broadcasting via Satellite.
Multi-Channel Signature Calculator
IP
Analog TV Demodulator and Decoder IP (Silicon Proven)
The Analog TV Demodulator and Decoder IP core is extracted from a production chip and a silicon-proven IP core.