In-Depth: Making platform ASICs easier to use
Tim Daniels looks at how one manufacturer’s IP options are designed simplify matching Platform ASICs with the design specification
The sweet spot for Platform ASICs is when the volume costs of FPGA are excessive or when performance/density is important, but the high fixed costs of a full cell-based ASIC cannot be justified (fig 1).
Gartner Dataquest defines “Platform ASICs” as products where up to half the die is predetermined, pre-verified intellectual property (IP), leaving the customer to customise (program) only a portion of it. By far the most popular Platform ASIC type is the embedded array, where the critical IP functions are pre-designed leaving the customer to configure memory and customisable logic via final metal layers. But what IP should be pre-designed and how can the customisable logic produce maximum performance without extensive design time?
Click here to read more .....
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related Articles
- What platform ASICs are and when to use them
- Platform ASICs stake the middle ground
- The virtual vehicle: making power management easier
- Which DDR SDRAM Memory to Use and When
Latest Articles
- Hardware-managed heterogeneous high-bandwidth memory and flash in LLM inference systems
- LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension
- A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node
- Automated Estimation of MBIST Area and Test Time in Heterogeneous Memory IPs via Stacked Ensemble Framework
- VIPER: Architecture-Aware Performance Modeling for Processing-in-Memory Design-Space Exploration