Which DDR SDRAM Memory to Use and When
By Vadhiraj Sankaranarayanan, Synopsys
Overview
Memory performance is a critical component for achieving the desired system performance in a wide range of applications from cloud computing and artificial intelligence (AI) to automotive and mobile. Dual Data Rate Synchronous Dynamic Random-access Memory (DDR SDRAM) or simply DRAM has emerged as the de facto memory technology for the main memory due to its many advantages: high density with simplistic architecture using a capacitor as a storage element, low latency and high performance, almost infinite access endurance, and low power. The Joint Electron Device Engineering Council (JEDEC) has defined several DRAM categories of standards to meet the power, performance, and area requirements of each application. Selecting the right memory solution is often the most critical decision for obtaining the optimal system performance. This whitepaper provides an overview of the JEDEC memory standards to help SoC designers select the right memory solution, including IP, that best fits their application requirements.
Related Semiconductor IP
- UALink 200G v1.0 Verification IP
- CCSDS SCCC Demapper and Turbo Decoder
- NPU IP
- JPEG XL Encoder
- I2C Master/Slave Controller Core
Related Articles
- Implementing custom DDR and DDR2 SDRAM external memory interfaces in FPGAs (part 1)
- Memory Design Considerations When Migrating to DDR3 Interfaces from DDR2
- Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM
- What platform ASICs are and when to use them
Latest Articles
- BARE-AI: Bit-Flip Attack Resilience in AI Hardware through Built-in Performance Monitors
- RFChipAgent: Multi-Agentic AI Flow for Analog/RF Chip Design
- Anechoic: Onsager-Corrected Parallel Annealing for Sub-0.1 ms Dense Max-Cut on an FPGA
- Power, Performance, and Area of HPC-Based Malware Detectors: An FPGA and Open-PDK ASIC Study
- Terracotta: Enabling the Adoption of New DRAM Techniques via a Flexible DRAM Interface and Memory Controller