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Vendor:
Synopsys, Inc.
Category:
CPU
ARC-V RHX-100 dual-issue, 32-bit single-core RISC-V processor for real-time applications
The Synopsys ARC-V™ RHX-100 series processors feature a dual-issue, 32-bit superscalar architecture for use in applications where…
Overview
The Synopsys ARC-V™ RHX-100 series processors feature a dual-issue, 32-bit superscalar architecture for use in applications where real-time performance is required. The cores offer outstanding performance delivering with a small area footprint and low power consumption.
The ARC-V RHX-100 processors are based on the RISC-V instruction set architecture (ISA). The processors feature a 34-bit physical address
space defined by the RISC-V Sv32 MMU. For applications requiring higher performance, the multi-core RHX-105 and RHX-105V are available with up to 16 CPU cores and up to 16 hardware accelerators in the processor cluster. RISC-V vector extensions (RVV) are available in the RHX-100V (single core) and RHX-105V (multi-core) processors.
The ARC-V RHX-100 features level 1 (L1) instruction and data cache and close coupled memory (CCM) and is optimized for use in high-performance real-time embedded applications.
The ARC-V RHX-100 processors are based on the RISC-V instruction set architecture (ISA). The processors feature a 34-bit physical address
space defined by the RISC-V Sv32 MMU. For applications requiring higher performance, the multi-core RHX-105 and RHX-105V are available with up to 16 CPU cores and up to 16 hardware accelerators in the processor cluster. RISC-V vector extensions (RVV) are available in the RHX-100V (single core) and RHX-105V (multi-core) processors.
The ARC-V RHX-100 features level 1 (L1) instruction and data cache and close coupled memory (CCM) and is optimized for use in high-performance real-time embedded applications.
Key features
- High-speed, 32-bit, dual-issue, 10-stage pipeline
- Multicore support for up to 16 CPUs and up to 16 user hardware accelerators per processor cluster
- Optional enhanced RISC-V Sv32 MMU with support for Linux and SMP Linux
- 4 KB to 128 KB instruction and data L1 cache
- Up to 16 MB cluster cache / shared memory
- Up to 16 MB instruction and data closely coupled memory (CCM)
- Real-time enhanced virtualization with 3-stage memory protection unit for OS needs (L1), for VM isolation (L2) and for system level isolation (L3). 128-bit loads and stores per clock
- Radix-4 hardware divider
- Up to 2x Advanced Platform Level Interrupt Controllers (APLIC) each supporting up to 1023 wired interrupts for a maximum of 2046 interrupts
- Native ARM® AMBA® AXI interfaces™, AHB-Lite™ and CHIinterfaces
- JTAG and Compact JTAG (cJTAG) debug interface
Benefits
- Dual-issue, 32-bit processors for high- performance real-time applications
- Multicore Processor versions with up to 16 CPU cores and up to 16 hardware accelerators
- Based on the RISC-V ISA, leveraging standard 32-bit protocols (and extensions)
- Real-time enhanced virtualization
- High degree of configurability
- Support for custom instructions
- Support for up to 16 MB of closely coupled memory and direct mapping of peripherals
- Optional MMU with hardware page table walk and up to 16 MB page sizes
- Optional support for RISC-V defined vector extensions (RVV)
- Real-time Trace (RTT) provides real-time trace debugging features
Applications
- Industrial: Robotics, Medical devices, factory automation
- Automotive: Domain controller, infotainment, safety management
- Consumer: Display control, laser printers, soft modems
- Storage: Solid state drive (SSD) controller, computational storage
- Networking: NIC, Ethernet switches, wireless access (WAP)
What’s Included?
- The Synopsys ARC-V RHX-100 processors are delivered in Verilog HDL in the ARChitect IP Library. The HDL is configurable by the user and output from the ARChitect IP Configurator tool. To test that the product performs as expected, a basic testbench of Customer Confidence Tests (CCT) is included
Specifications
Identity
Part Number
dwc_arcv_rhx100_core
Vendor
Synopsys, Inc.
Type
Silicon IP
Compute
CPU Architecture
RISC-V
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about CPU IP cores
What is ARC-V RHX-100 dual-issue, 32-bit single-core RISC-V processor for real-time applications?
ARC-V RHX-100 dual-issue, 32-bit single-core RISC-V processor for real-time applications is a CPU IP core from Synopsys, Inc. listed on Semi IP Hub.
How should engineers evaluate this CPU?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.