Priority-Aware Deficit Round Robin for AXI4 Bandwidth Fairness in ASAP-7nm Process

By Tasmin Khan ¹, Tishna Sabrina ², Ch. Md. Rakin Haider ^1
1 Bangladesh Univ. of Eng. & Tech.
² Univ. of Asia Pacific

Abstract

Modern systems-on-chip place real-time clients, processor cores and bulk data engines on the same AXI4 interconnect, where they contend for shared slaves. AXI4 fixes the ordering rules and carries a 4-bit quality of service (QoS) field, but leaves the service policy to the implementer, and that policy determines how long each master waits and how much bandwidth it receives once a slave saturates. We propose a QoS-aware deficit round robin (DRR) architecture that charges each grant in beats, and benchmark it against two architectures built behind the same port list: round robin, and QoS priority with anti-starvation aging. Charging in beats recovers bandwidth fairness while leaving every burst whole, so the address phase is issued once and locality for memory access is preserved. All three are driven by the same deterministic traffic generator and taken from RTL to GDSII on the ASAP7 7-nm predictive PDK. Under a 1:16 burst-length mismatch, the round robin and QoS architectures both hold the beat ratio between the two competing masters at 1:16, while our design brings it to 1:1 at full load. Mean read latency for the priority master falls from 95 cycles under round robin to 67 with QoS and 37 with QoS-aware DRR. At 500 MHz this serves the priority master in 74 ns against 190 ns. The measurements give a per-policy price and a traffic-based guide for choosing among the three.

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