Debunking myths about analog IP at 28 nm
Manuel Mota, Synopsys
12/3/2012 12:37 PM EST
The economics of system-on-chip development are objective and well understood. Industry-wide trends set the stage for integrating more functions into a SoC, which then drives the scaling down of process technology nodes. In the resulting product, all of the previous product’s functionality is implemented while more functional blocks are added to build increasingly complex functionality. This trend is not questioned - it is an axiom.
Register transfer logic (RTL) is agnostic to the process technology node, so porting digital functionality is not perceived as problematic. However, analog functionality is perceived as more challenging because of its closer dependency on the process characteristics. At each new node, the debate regarding whether or not to integrate analog IP into the SoC is rekindled until the economics validate the integration. Successful mixed-signal SoCs in all previous process technology nodes have demonstrated this cycle despite the persistence of three myths around the economics of analog block implementation in advanced process technologies.
These three myths deserve to be analyzed to better understand why they are erroneous.
To read the full article, click here
Related Semiconductor IP
- Root-of-Trust IP - High-Assurance Security for Advanced and Regulated Applications
- Root-of-Trust IP - Enhanced-Assurance, Configurable Security for Scalable Semiconductor Designs
- Root-of-Trust IP - Compact, Configurable Security for Flexible Semiconductor Designs
- 100-10Gbps Ethernet MAC Controller
- SD Card Controller
Related Articles
- Density Requirements at 28 nm
- Fully depleted silicon technology to underlie energy-efficient designs at 28 nm and beyond
- Analog IP to protect SoC from side-channel attacks
- MEGATRON: a 28nm Analog PCM CiM/Digital System-on-Chip for Edge GenAI at 57.5 TOPS/W and 1.52 Mparam/mm²
Latest Articles
- LLM Agent-Based Design of RISC-V CPUs with FPGA-in-the-Loop Evaluation
- Automated Multi-Line Bug Repair Using Model Checker Aided LLMs: A Case Study on RISC-V Processors
- Cryogenic Recharacterization of a Commercial 22 nm FD-SOI Foundry Standard-Cell Library
- A 105 MS/s 4.18 nJ/inference 0.765 mm² Mixed-Signal Streaming ML Engine for Wireless Baseband in 12LP+ FinFET
- Agentic AI for Heterogeneous System Design Across Chip, Scale-Up, and Scale-Out Domains