MEGATRON: a 28nm Analog PCM CiM/Digital System-on-Chip for Edge GenAI at 57.5 TOPS/W and 1.52 Mparam/mm²
By Alessandro Nadalini 1, Angelo Garofalo 1, Lorenzo Greco 1, Andrea Belano 1,2, Alessio Antolini 1, Francesco Zavalloni 1, Andrea Lico 2, Riccardo Zurla 3, Emanuela Calvetti 3, Luigi Croce 3, Marco Pasotti 3, Alessandro Cabrini 4, Eleonora Franchi Scarselli 1, Davide Rossi 1,2, Francesco Conti 1,2
1 University of Bologna, Italy,
2 Chips-IT, Italy,
3 STMicroelectronics, Italy,
4 University of Pavia, Italy

Abstract
We present MEGATRON, a heterogeneous Edge GenAI System-on-Chip in 28nm FD-SOI CMOS technology combining a non-volatile analog in-memory-computing engine based on a 4Mi-cell phase-change memory (PCM) array with a digital RISC-V-based flexible neural processing unit. MEGATRON demonstrates up to 3.5 TOPS/W using the RISC-V processors and 57.5 TOPS/W with PCiM, at a storage density of 1.52 Mparam/mm² with 4-bit effective weight precision.
To read the full article, click here
Related Semiconductor IP
- NPU
- RISC-V-Based, Open Source AI Accelerator for the Edge
- NPU IP for Embedded ML
- NPU IP
- Highly scalable inference NPU IP for next-gen AI applications
Related Articles
- Tools get incomplete grade for analog IP creation
- System-on-chip market to hit 1.3 billion units in 2004, says new report
- Panel ponders cost of programmable system-on-chip
- IC Physical Design: Portable Layout and Simulation Technigues for ADSL Analog Devices
Latest Articles
- A 105 MS/s 4.18 nJ/inference 0.765 mm² Mixed-Signal Streaming ML Engine for Wireless Baseband in 12LP+ FinFET
- Agentic AI for Heterogeneous System Design Across Chip, Scale-Up, and Scale-Out Domains
- Minimum RISC-V: Maximum FPGA Efficiency
- The Era of Vibe Tapeout: Dark Age or Golden Age for Analog Circuit Design?
- Understanding the Power Consumption of Modern High Bandwidth Memory: Experimental Analysis and Modeling Using Real HBM2 DRAM Chips