A novel 3D buffer memory for AI and machine learning
January 27, 2025
Semiconductor IP Articles Archive - Page 12 of 228
Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures
January 27, 2025
Assessing Design Space for the Device-Circuit Codesign of Nonvolatile Memory-Based Compute-in-Memory Accelerators
January 27, 2025
The SoC design: What’s next for NoCs?
January 24, 2025
Streamlining SoC Design with IDS-Integrate™
January 23, 2025
Linearity Analysis of Source-Degenerated Differential Pairs for Wireline Applications
January 22, 2025
How Ultra Ethernet And UALink Enable High-Performance, Scalable AI Networks
January 20, 2025
Expanding the Horizon of System Monitoring with the Arm SMCF
January 20, 2025
Monolithic 3D FPGAs Utilizing Back-End-of-Line Configuration Memories
January 19, 2025
Reimagining AI Infrastructure: The Power of Converged Back-end Networks
January 15, 2025
40G UCIe IP Advantages for AI Applications
January 13, 2025
Recent progress in spin-orbit torque magnetic random-access memory
January 13, 2025
What is JESD204C? A quick glance at the standard
January 9, 2025
Open-Source Design of Heterogeneous SoCs for AI Acceleration: the PULP Platform Experience
January 9, 2025
The Growing Imperative Of Hardware Security Assurance In IP And SoC Design
January 8, 2025
Tackling Network-on-Chip (NoC) Scaling Challenges with a System-technology Co-optimization Approach
January 7, 2025
Last-Time Buy Notifications For Your ASICs? How To Make the Most of It
January 6, 2025
Optimized Clocking Solutions for High-Performance Die-to-Die Interfaces
January 6, 2025
The backpropagation algorithm implemented on spiking neuromorphic hardware
December 18, 2024
The Benefits of a Multi-Protocol PMA
December 16, 2024
