How Cadence and TSMC Are Accelerating AI Silicon Design at Advanced Nodes

By Cadence

July 13, 2026

Designing AI silicon for increasing AI/HPC workloads at advanced nodes has become one of the toughest challenges in the semiconductor industry. Escalating goal-driven PPA, reliability, and productivity-optimization demands are converging as development cycles continue to compress. At advanced nodes, even small inefficiencies can lead to costly design iterations, schedule slips, and delayed market entry.

To address these challenges, Cadence and TSMC have expanded their collaboration, focusing on accelerating the AI-driven semiconductor innovation through advanced design flows for leading-edge AI silicon.

This post opens a four-part series exploring how the expanded Cadence–TSMC collaboration helps accelerate AI silicon design innovation. It frames the collaboration at advanced-node design to reduce iterations and improve correlation for DTCO-focused advanced AI and HPC designs—accelerating time to silicon with greater confidence. In the posts ahead, we’ll look more closely at the role of certified flows and signoff-ready methodology, the importance of silicon-proven IP, the latest enablement across advanced nodes, including TSMC’s N3, N2, A16^TM, and A14, and the customer momentum already underway at 3nm and 2nm.

Expanding a Longstanding Cadence–TSMC Collaboration

As compute demands expand across IoT, smartphones, AI, HPC, and automotive applications, mutual customers need to design efficiently and confidently on TSMC’s cutting-edge technologies and advanced packaging platforms.

The long-standing Cadence collaboration with the TSMC Open Innovation Platform® (OIP) ecosystem directly addresses this need by delivering certified digital, analog, and signoff solutions that meet required design criteria while helping improve power, performance, area, and productivity at TSMC advanced process technologies.

Through partnership with TSMC, Cadence is advancing its “Design for AI and AI for Design” strategy to reduce time-to-silicon and time-to-revenue by combining certified EDA flows, silicon-proven IP, agentic AI technologies, and accelerated computing as a workforce multiplier.

The collaboration spans the full design lifecycle, from front-end synthesis through implementation, multiphysics analysis, and signoff.  It will help customers reduce iterations and improve correlation for DTCO-focused advanced AI and HPC designs, accelerating time-to-silicon with greater confidence.

Working with TSMC, Cadence is making design flows, optimization engines, and signoff infrastructure “agent-ready,” so AI systems can combine domain reasoning with physics-based analysis to drive convergence for designs at TSMC advanced process technologies.

Certified Design Flows to Reduce Iterations and Accelerate Time to Market

At advanced nodes, design iterations are increasingly expensive, and gaps in correlation between implementation and signoff can quickly derail schedules. A central focus of the Cadence–TSMC collaboration is the delivery of TSMC‑certified, end‑to‑end EDA flows that improve consistency and predictability throughout the design process.

These TSMC-certified flows help teams converge earlier on tapeout‑quality results by reducing late‑stage surprises and minimizing rework or design iterations. Cadence introduced early detailed routing technology to enable improved correlation between early exploration and final signoff, delivering more predictable closure of performance, power, and reliability targets for advanced AI and HPC designs. This approach is especially critical for DTCO‑focused environments, where tight coordination between design and process is essential. Cadence collaborated with TSMC to develop completely new implementation and signoff flows to support new advanced node innovations, such as backside power routing.

End-to-End, Signoff-Ready Methodology for AI Silicon

Modern AI silicon designs increasingly span digital logic, custom and analog circuitry, power and signal integrity, thermal and electromagnetic effects, and heterogeneous integration. To support this complexity across SoC design, Cadence and TSMC deliver a signoff‑ready, end‑to‑end design methodology aligned with the requirements of advanced AI and HPC applications. This methodology integrates:

• Digital implementation (Innovus Implementation System)
• Custom and analog design and simulation (Virtuoso Studio and Spectre Simulation Platform)
• Signoff technologies, including Tempus Timing and ECO Solutions, Quantus Extraction Solution, Liberate Characterization Portfolio, and Pegasus Verification System
• Thermal analysis, power integrity, and electromagnetic analysis with Celsius Thermal Solver, Voltus IC Power Integrity Solution, and EMX Planar 3D Solver

• Additionally, the Genus Synthesis Solution is enabled for TSMC process technologies and ongoing collaboration is under way on Clarity 3D Solver.

By unifying these capabilities within certified methodologies, the collaboration supports predictable convergence from architecture through signoff, helping teams manage advanced‑node complexity with greater confidence.

Complementing the flows is Cadence’s silicon‑proven IP portfolio for advanced nodes, including high‑bandwidth memory and high‑speed interface technologies tailored to AI system requirements.

Focus on Advanced Nodes: TSMC’s N3, N2, A16^TM, and A14

The expanded collaboration spans multiple advanced process generations, enabling continuity as customers plan multi‑generation AI roadmaps.

• N3: Cadence delivers certified end-to-end flows, and Cadence’s Artisan foundation IP advanced‑node portfolio is in production designs using TSMC N3 process technologies
• N2: Cadence delivers certified end‑to‑end EDA flows and a rich silicon‑proven IP portfolio optimized for TSMC N2P
• A16^TM: Cadence’s digital, custom/analog, and signoff platforms are certified for TSMC A16, supporting advanced AI and HPC designs
• A14: Cadence and TSMC are engaged in ongoing collaboration on TSMC A14 PDK enablement to accelerate future convergence toward tapeout‑quality results

Across these nodes, Cadence and TSMC are aligning certified methodologies and design infrastructure, helping customers adopt advanced processes with reduced risk.

Explore Cadence IP:

• 224G-LR SerDes PHY

Customer Momentum at 3nm and 2nm

Strong customer adoption underscores the impact of the expanded Cadence–TSMC collaboration. Across the AI and HPC ecosystem, companies are actively designing silicon on TSMC’s 3nm and 2nm technologies, leveraging certified flows and silicon‑proven IP.

This momentum reinforces the importance of signoff‑ready, end‑to‑end infrastructure in enabling faster, more confident delivery of next‑generation AI silicon at advanced nodes.

Accelerating AI Silicon Design with Greater Confidence

As AI and HPC workloads continue to push the limits of semiconductor design, success at advanced nodes depends on reducing design iterations, improving correlation, and enabling predictable execution across the full design lifecycle. Through their expanded collaboration, Cadence and TSMC are delivering the certified, end‑to‑end foundation required to meet these demands, supporting advanced AI silicon across TSMC’s N3, N2, A16^TM, and A14.

With strong customer momentum already underway at TSMC’s 3nm and 2nm technologies, the collaboration is helping semiconductor teams accelerate innovation and bring next‑generation AI silicon to market with greater confidence.

Learn more about the expanded Cadence–TSMC collaboration in the next blog post on the importance of silicon-proven IP from Cadence that helps reduce integration uncertainty, improve correlation between implementation and signoff, and support smoother convergence toward tapeout.