How AI Is Enabling Digital Design Retargeting to Maximize Productivity
Chips below 5nm are the fastest growing part of the semiconductor market, fueling today’s leading consumer devices and data centers. Not only are these devices getting smaller, but they’re also packed with greater functionality. Unfortunately, growing chip complexity is converging with shortages in technical talent, making it harder for companies to meet their aggressive market requirements.
The challenge is on for companies to drive greater efficiency and productivity into their organizations, and artificial intelligence (AI) has emerged as one way to do this. AI is already proving to be quite successful in helping to optimize designs to meet stringent power, performance, and area (PPA) targets. As global compute demand continues to outpace Moore’s law, companies need to figure out how to effectively leverage larger scale designs that are still viable and retarget them to similar process nodes that have available capacity, while taking advantage of the potential performance and power efficiency gains of a new node.
Such retargeting projects are often executed as a completely new project, with timelines and engineering resources matching those of the original project. The time and effort required has been impacting time to market, cost and, therefore, the viability of such product and business maneuvers.
Today, AI can make this chip design retargeting effort a more streamlined, cost-efficient reality.
To read the full article, click here
Related Semiconductor IP
Related Blogs
- How to Maximize PCIe 6.0's Advantages with End-to-End PCIe Design Solutions
- How is RISC-V’s open and customizable design changing embedded systems?
- The 5 Biggest Challenges in Modern SoC Design (And How to Solve Them)
- Reimagining Chip Design - From Spec to Signoff with Cadence AI Super Agents
Latest Blogs
- Designing for What Comes Next in AI
- Secure boot on Efinix Titanium Ti60: Getting started with KiviBoot-Tiny
- How Long Does It Take to Port a New AI Model? Minutes Now, and Falling
- PCI Express Security and TEE Integration, Part 1 - Establishing Trust
- World Models at the Edge, in Real Time: V-JEPA 2.1 on the Quadric GPNPU