Circuit Design in FinFET Technologies: Evolution or Revolution?

By EETimes

November 28, 2013

Carey Robertson, Mentor Graphics
EETimes (11/27/2013 01:48 PM EST)

All of the major foundries have announced FinFET technologies for their most advanced processes. Intel introduced this transistor at the 22 nm node, TSMC for their 16 nm process, and Samsung and Globalfoundries are introducing it for their 14 nm processes. As with any new process technology, the most important question to an IC designer is "What does this mean to me?"

New, smaller process technologies means the designer will benefit from reduced power consumption, better area utilization, and other traditional improvements that come from semiconductor scaling. Along with those advantages, there is the learning cost to understand the new design rules, parametric differences, and new or enhanced methodologies that must be implemented to design at the new node. The benefits have always justified the costs until now. Will that still be true with FinFETs?

Like any other new technology, FinFET processes have a cost associated with learning how to design with them. Because FinFETS are a completely different transistor, the question is -- will this change be evolutionary (typical learning cost) or revolutionary (significant learning cost). The answer depends on your perspective.

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