Accelerating Memory Debug
February 12, 2015
Following on his recent talk about Key Advantages of Synopsys Memory VIP Architecture, here Synopsys R&D Director Bernie DeLay talks about protocol-aware debug for memories: a single environment to simultaneously visualize transactions, state machines, and memory arrays
Related Semiconductor IP
- NPU IP
- JPEG XL Encoder
- I2C Master/Slave Controller Core
- NVMe Validation Test Suite
- Hybrid Memory Cube Verification IP
Related Blogs
- PCIe: Accelerating Debug
- Simplifying Debug of Memory Models
- Reduce Protocol Debug Time with Memory VIP
- How to Reduce Memory Model Debug Time
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