Reduce Protocol Debug Time with Memory VIP
September 23, 2019
Looking for ways to reduce debug cycles to quickly root cause the issues in your Memory Controller/PHY and Subsystem Verification Project?
If you have not already deployed Protocol Aware Debug capabilities, learn why these are recommended…
Key attributes of the Memory Protocol Aware Debug flow:
- Protocol-centric debug enables user to quickly understand protocol activity, identify bottlenecks and quickly find and debug unexpected behavior
- Error, warning and messaging annotation within the protocol view to quickly root cause
- Graphical view of transaction, bank states, memory content, and handshaking with immediate access to context specific detailed information
- Lock-step linking to simulator-trace views (waveforms) enabling easy debug at any level of abstraction
Synopsys Memory VIP supports the latest ratified and draft specifications from standards organizations such as JEDEC (for DDR5, LPDDR5, DFI 5.0, HBM3, GDDR6, and NVDIMM-P/N), ONFi, SD, and SPI along with native integration and optimizations with our VCS and Verdi tools.
To read the full article, click here
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related Blogs
- How to Reduce Memory Model Debug Time
- Validating UPLI Protocol Across Topologies with Cadence UALink VIP
- PCIe Gen4 - VIP/IP Solution with Protocol-Aware Debug and Source Code Test Suites
- Overcoming the Protocol Debug Challenge
Latest Blogs
- Beyond Trusted: What the NSA’s New Guidance Means for Hardware Security
- A scalable, shader-programmable vector graphics GPU core for low-power MCUs
- Navigating ISO 26262 Part 11: A Guide for Semiconductor Architects
- Embedded Security explained: Digital signatures
- Hardware security verification must go beyond functional testing