PLL IP Listing

The 1G/10G Ethernet PHY Intel® FPGA Intellectual Property (IP) core supports functionality of both the standard physical coding s…

• Single-Protocol PHY

The DDR IP Mixed-Signal MRDIMM DDR5 PHY and DDR5/4 Combo PHY provide turnkey physical interface solutions for ICs requiring acces…

• Controller + PHY
• DDR5

Short-range radar has many potential applications, such as gesture control, contactless vital-signs monitoring, presence detectio…

• RF Transceiver

The WEAADC12BHS22G is a 12-bit Successive Approximation Analog-to-Digital Converter (ADC) that supports both single-ended and dif…

• 12 Bit
• GlobalFoundries
• 22nm
• FDX

IGAHBMX03A is a HBM3 (High Bandwidth Memory) PHY IP compliant to the JEDEC HBM3 DRAM Specification Rev 0.95.

• Controller + PHY + 1
• TSMC
• 7nm
• N7FF

With sophisticated architecture and technology, the USB3.1 transceiver IP with PMA and PCS layer is designed for low power and hi…

• Single-Protocol PHY

With sophisticated architecture and technology, JESD204B /204C IP with PHY and MAC layer is designed for low power and high perfo…

• JESD204

RapidIO is a high performance, low pin count, packet switched, full duplex, system level interconnect architecture.

• RapidIO

With sophisticated architecture and technology, the SerDes PHY IP with PMA and PCS layer is designed for low power and high perfo…

• Single-Protocol PHY

This MIPI D-PHY IP is designed to compliant with the MIPI D-PHY v1.2 specifications.

• Multi-Protocol PHY

The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).

• TSMC
• 5nm
• N5A

The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).

• PCIe Gen5
• Samsung
• 8nm
• 8LPP

The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).

• PCIe Gen4
• Samsung
• 7nm
• SF7LPP

The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).

• TSMC
• 5nm
• N5

The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).

• PCIe Gen3
• Samsung
• 8nm
• 8LPP

The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).

• PCIe Gen4
• Samsung
• 8nm
• 8LPP

The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).

• PCIe Gen3
• Samsung
• 7nm
• SF7LPP

The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).

• PCIe Gen3
• Samsung
• 28nm
• FDS

The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).

• TSMC
• 28nm
• HPC+

The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).

• TSMC
• 16nm
• FFC