Low Power PCIe Gen3 PHY on TSMC CLN16FFC

The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PCIe 3.0 PHY operates at 2.5Gbps, 5Gbps, and 8Gbps. The PHY additionally features an interface capability that allows integration with other customer-designed serial protocol PCS layers. The PMA is delivered as a hard macro while the fully-synthesizable soft PCS includes performing all necessary calibration and self-test functions. The universal PHY architecture allows forming arbitrarily wide efficient links by being independent of the need for a common CMU.

• Industry leading low power PMA macro – 36mW per lane at 8Gbps (4.5mW/Gbps), inclusive of Tx and Rx PLLs, termination, bias, etc.
• Compact form factor – 0.133 mm2 total active area per lane
• Supported protocols include: PCIe Gen3/2/1, SATA3/2/1, XAUI/RXAUI, SGMII
• Finely configurable receiver impedance, CTLE gain and bandwidth, with fully adaptive CTLE and 5- tap DFE
• Finely configurable driver impedance, amplitude and 3-tap FFE
• Supports L1 sub-states and all power-down modes
• Minimal latency – 3 UI between parallel transfer and serial transmission
• Single-lane macro scalable to unlimited link width – x1, x2, x4, x8, x16, etc.
• Multi-orientation macros of 4, 8 and 16 lane SERDES are available for most common metal stacks
• Test support features such as ac-JTAG, near-end loopback, reverse loopback, PRBS generator+checker, PLL bypass modes, etc.
• PIPE Compliant PCS with programmable PIPE frequencies
• Supports Bifurcation, lane/link powerdown, SRNS, SRIS
• Supports industry standard third-party controllers for PCIe
• Low pin-count and suitable for a variety of flip-chip packages when paired with onchip T-coils
• Metallization scheme and pad/bump structures customizable to specifications